9.7.2 VE_SysRegs component

This section describes the VE system registers component.

VE_SysRegs - about

This LISA+ component is a model of the VE status and system control registers.

VE_SysRegs - ports

This section describes the ports.

Table 9-15 VE_SysRegs ports

Name Protocol Type Description
cb[0-1] VECBProtocol Master The Configuration Bus (CB) controls the power and reset sequence.
clock_24Mhz ClockSignal Slave Reference clock for internal counter register.
clock_100Hz ClockSignal Slave Reference clock for internal counter register.
clock_CLCD ClockRateControl Master The clock for the LCD controller.
lcd LCD Master Multimedia bus interface output to the LCD.
leds ValueState Master Displays state of the SYS_LED register using the eight colored LEDs on the status bar.
mmb[0-2] LCD Slave Multimedia bus interface input.
mmc_card_present StateSignal Slave Indicates the presence of a MultiMedia Card (MMC) image.
pvbus PVBus Slave Slave port for connection to PV bus master/decoder.
system_reset Signal Master Signal to the platform a complete system reset. Writes to the System Configuration registers can trigger the reset signal.
user_switches ValueState Master Provides state for the eight User DIP switches on the left side of the CLCD status bar, equivalent to switch S6 on VE hardware.

VE_SysRegs - parameters

This section describes the parameters.

Table 9-16 VE_SysRegs parameters

Name Type Default value Description
exit_on_shutdown bool false Used to shut down the system. When true, if software uses the SYS_CFGCTRL function SYS_CFG_SHUTDOWN, then the simulator shuts down and exits.a
mmbSiteDefault int 0x1 Default MultiMedia Bus (MMB) source (0=motherboard, 1=daughterboard 1, 2=daughterboard 2).
sys_proc_id0 int 0x0c000000 Processor ID register at CoreTile Express Site 1.
sys_proc_id1 int 0xff000000 Processor ID at CoreTile Express Site 2.
tilePresent bool true Tile fitted.
user_switches_value int 0 User switches.

VE_SysRegs - registers

This section describes the configuration registers.

Table 9-17 VE_SysRegs registers

Name Offset Access Description
SYS_ID 0x00 Read/write System identity.
SYS_SW 0x04 Read/write Bits[7:0] map to switch S6.
SYS_LED 0x08 Read/write Bits[7:0] map to user LEDs.
SYS_100HZ 0x24 Read only 100Hz counter.
SYS_FLAGS 0x30 Read/write General purpose flags.
SYS_FLAGSCLR 0x34 Write only Clear bits in general purpose flags.
SYS_NVFLAGS 0x38 Read/write General purpose non-volatile flags.
SYS_NVFLAGSCLR 0x3C Write only Clear bits in general purpose non-volatile flags.
SYS_MCI 0x48 Read only MCI.
SYS_FLASH 0x4C Read/write Flash control.
SYS_CFGSW 0x58 Read/write Boot select switch.
SYS_24MHZ 0x5C Read only 24MHz counter.
SYS_MISC 0x60 Read/write Miscellaneous control flags.
SYS_DMA 0x64 Read/write DMA peripheral map.
SYS_PROCID0 0x84 Read/write Processor ID.
SYS_PROCID1 0x88 Read/write Processor ID.
SYS_CFGDATA 0xA0 Read/write Data to be read/written from/to motherboard controller.
SYS_CFGCTRL 0xA4 Read/write Control data transfer to motherboard controller.
SYS_CFGSTAT 0xA8 Read/write Status of data transfer to motherboard.

VE_SysRegs - verification and testing

This component was tested as part of the Versatile™ Express model.


For more information on the SYS_CFGCTRL function values, see the Motherboard Express μATX V2M-P1 Technical Reference Manual.

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