3.9.44 PL110_CLCD

ARM PrimeCell Color LCD Controller(PL110). This model is written in LISA+.

PL110_CLCD contains the following CADI targets:

  • ClockTimerThread
  • ClockTimerThread64
  • PL110_CLCD
  • PL11x_CLCD
  • SchedulerThread
  • SchedulerThreadEvent

PL110_CLCD contains the following MTI components:

About PL110_CLCD

This implementation provides a register model of the LCD controller.

You can connect the model through a framebuffer port to a visualization component, for example, so that LCD output can be viewed.

The implementation is optimized for situations where the majority of the framebuffer does not change. For instance, displaying full-screen video results in significantly reduced performance. Rendering pixel data into an appropriate form for the framebuffer port (rasterization) can also take a significant amount of simulation time. If the pixel data are coming from a PVBusSlave region that has been configured as memory-like, rasterization only occurs in regions where memory contents are modified.

Table 3-373 Ports

Name Protocol Type Description
clk_in ClockSignal Slave Master clock input, typically 24MHz, to drive pixel clock timing.
control Value Slave Auxiliary control register 1.
display LCD Master Connection to visualization component.
intr Signal Master Interrupt signaling for flyback events.
pvbus PVBus Slave Slave port for register access.
pvbus_m PVBus Master DMA port for video data.

Table 3-374 Parameters for PL11x_CLCD

Name Type Default value Description
pl11x_clcd.disable_snooping_dma bool 0x0 Disable DMA snooping
pl11x_clcd.pixel_double_limit int 0x12c Minimum LCD pixel width before display will be zoomed
pl11x_clcd.pl11x_behavior int 0x0 Define PL11x behaviour. 0 for PL110, 1 for PL111

Table 3-375 Parameters for PL110_CLCD

Name Type Default value Description
disable_snooping_dma bool 0x0 Disable DMA snooping
pixel_double_limit int 0x12c Minimum LCD pixel width before display will be zoomed
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