3.2.4 PVBusExclusiveMonitor

Global exclusive monitor. This model is written in C++.

PVBusExclusiveMonitor contains the following CADI targets:

  • PVBusExclusiveMonitor

PVBusExclusiveMonitor contains the following MTI components:

Table 3-41 Ports

Name Protocol Type Description
excl_cleared Signal Master Exclusive monitor clear signal port.
pvbus_m PVBus Master Bus master port.
pvbus_s PVBus Slave Bus slave port.

Table 3-42 Parameters for PVBusExclusiveMonitor

Name Type Default value Description
apply_access_width_criteria_to_non_excl_stores bool 0x1 Apply the given exclusive store width matching criteria to non-exclusive stores
clear_on_strex_address_mismatch bool 0x1 Whether monitor is cleared when strex fails due to address mismatch
enable_component bool 0x1 Enable component
log2_granule_size int 0x0 log2 of address granule size
match_access_width bool 0x0 Fail STREX if not the same access width as LDREX
match_secure_state bool 0x1 Treat the secure state like an address bit
monitor_access_level int 0x0 0: Monitor all accesses, 1: Monitor all accesses except WriteBack, 2: Only monitor accesses with memory type NonCacheable or Device
monitor_non_excl_stores bool 0x0 Monitor non-exclusive stores from the same master
number_of_monitors int 0x8 Number of monitors
shareability_domain int 0x3 Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system)
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