3.4.31 ARMCortexM4CT

ARMCortexM4CT CPU component. This model is written in C++ and models version r0p0 of the RTL.

ARMCortexM4CT contains the following CADI targets:

  • ARM_Cortex-M4

ARMCortexM4CT contains the following MTI components:

Differences between the model and the RTL

This component has the following differences from the corresponding revision of the RTL implementation:

  • The Wakeup Interrupt Controller (WIC) is not implemented.
  • Power control is not implemented. Powering down of the processor is not supported. The processor must still be clocked even if it has asserted the sleeping or sleepdeep signals.
  • Only the minimal level of debug support is provided (no DAP, FPB, DWT, or halting debug capability).
  • No debug-related components are implemented.
  • The unimplemented registers are the processor debug registers, system debug registers, debug interface port registers, TPIU registers, and ETM registers.
  • No support for ETM, TPIU, or HTM.
  • There is no supported equivalent of the RESET_ALL_REGS configuration setting in RTL (that forces all registers to have a well-defined value on reset).
  • Disabling processor features using the Auxiliary Control Register is not supported.
  • Only a single pvbus_m master port is provided. This combines the ICode, DCode, and System bus interfaces of the RTL. The external PPB bus is provided by the pv_ppbus_m master port.
  • In privileged mode, STRT and LDRT to the PPB region are not forbidden access.
  • The RTL implements the ROM table as an external component on the External Private Peripheral Bus. In the CT model, the ROM table is implemented internally as a fallback if an external PPB access in the ROM table address region aborts. This permits the default ROM table to be overridden (by implementing an external component connected to the external PPB to handle accesses to these addresses) without requiring every user of the processor to implement and connect a ROM table component.
  • Because the CT model does not provide a DAP port or halting debug capability, the dbgen signal is ignored.

Implementation of ITM in M-class models

This model has a parameter that enables partial support for Instrumentation Trace Macrocell (ITM). In hardware or RTL, trace data from ITM is sent in packets to the trace block serially using a single pin or wire. In the model, if it is enabled, the ITM trace data is output using an MTI trace source called ITM. The ITM trace source has an ITM_PACKET_TYPE field. The following table shows which packet types the model supports:

Table 3-155 ITM_PACKET_TYPE field values that the model supports

Field value Description Supported by model
ITM_SYNC Synchronization packet Not supported.
ITM_P_OVERFLOW Protocol: Overflow packet Not supported.
ITM_P_LOCAL_TIMESTAMP Protocol: Local timestamp packets Not supported.
ITM_P_GLOBAL_TIMESTAMP Protocol: Global timestamp packets Not supported.
ITM_P_EXTEN Protocol: Extension packet Not supported.
ITM_S_INSTRUMENTATION Source: Instrumentation packet Supported.
ITM_S_DWT_EVENT_COUNTER Hardware source: Event counter wrapping Not supported.
ITM_S_DWT_EXCEPTION Hardware source: Exception tracing Supported.
ITM_S_DWT_PC_SAMPLING Hardware source: PC sampling Not supported.
ITM_S_DWT_DATA_PC_TRACE Hardware source: DWT Data trace PC value Supported.
ITM_S_DWT_DATA_ADDRESS_TRACE Hardware source: DWT Data trace address value Supported.
ITM_S_DWT_DATA_DATA_TRACE Hardware source: DWT Data trace DATA value Supported.

Table 3-156 Ports

Name Protocol Type Description
ahb_ap PVBus Slave Debug AHB - core bus slave driven by the DAP.
auxfault Value Slave This is wired to the Auxiliary Fault Status Register.
bigend Signal Slave Configure big endian data format.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
currpri Value Master Current execution priority.
dbgen Signal Slave Disallow (DAP) debugger access.
edbgrq Signal Slave External debug request.
event Signal Peer This peer port of event input (and output) is for wakeup from WFE and corresponds to the RTL TXEV and RXEV signals.
fpudisable Signal Slave Configure core with no FPU on reset.
fpxxc Value Master Send the value of the FPXXC cumulative exception flags.
intisr[240] Signal Slave This signal array delivers signals to the NVIC.
intnmi Signal Slave Configure non maskable interrupt.
lockup Signal Master Asserted when the processor is in lockup state.
mpudisable Signal Slave Configure core with no MPU on reset.
poreset Signal Slave Raising this signal will do a power-on reset of the core.
pv_ppbus_m PVBus Master The core will generate External Private Peripheral Bus requests on this port.
pvbus_m PVBus Master The core will generate bus requests on this port.
sleepdeep Signal Master Asserted when the processor is in deep sleep.
sleeping Signal Master Asserted when the processor is in sleep.
stcalib Value Slave This is the calibration value for the SysTick timer.
stclk ClockSignal Slave This is the reference clock for the SysTick timer.
sysreset Signal Slave Raising this signal will put the core into reset mode (but does not reset the debug logic).
sysresetreq Signal Master Asserted to indicate that a reset is required.
ticks InstructionCount Master Port allowing the number of instructions since startup to be read from the CPU.

Table 3-157 Parameters for ARM_Cortex-M4

Name Type Default value Description
BB_PRESENT bool 0x1 Enable bitbanding
BIGENDINIT bool 0x0 Initialize processor to big endian mode
DBGLVL int 0x4 0: No debug; 1: Minimal debug; 2: Full debug without DWT address matching; 3: Full debug support with, DWT can compare data as well as address; 4: Experiential value, support debug feature but no breakpoint and watchpoint compare
LVL_WIDTH int 0x3 Number of bits of interrupt priority
NUM_IRQ int 0x10 Number of user interrupts
NUM_MPU_REGION int 0x8 Number of MPU regions
TRACE_LVL bool 0x1 Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
WIC bool 0x1 Include support for WIC-mode deep sleep
cpi_div int 0x1 divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 multiplier for calculating CPI (Cycles Per Instruction)
master_id int 0x0 Master ID presented in bus transactions
min_sync_level int 0x0 force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
scheduler_mode int 0x0 Control the interleaving of instructions in this processor (0=default long quantum, 1=low latency mode, short quantum and signal checking, 2=lock-breaking mode, long quantum with additional context switches near load-exclusive instructions, 3=ISSCompare)
semihosting-Thumb_SVC int 0xab T32 SVC number for semihosting
semihosting-cmd_line string "" Command line available to semihosting SVC calls
semihosting-cwd string "" Base directory for semihosting file access.
semihosting-enable bool 0x1 Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
semihosting-heap_base int 0x0 Virtual address of heap base
semihosting-heap_limit int 0x10700000 Virtual address of top of heap
semihosting-prefix bool 0x0 Prefix semihosting output with target instance name
semihosting-stack_base int 0x10700000 Virtual address of base of descending stack
semihosting-stack_limit int 0x10800000 Virtual address of stack limit
vfp-present bool 0x1 Set whether the model has VFP support
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