3.9.52 PL370_HDLCD

ARM PrimeCell HD Color LCD Controller (Nominal Designation PL370). This model is written in LISA+.

PL370_HDLCD contains the following CADI targets:

  • ClockTimerThread
  • ClockTimerThread64
  • PL370_HDLCD
  • SchedulerThread
  • SchedulerThreadEvent

PL370_HDLCD contains the following MTI components:


Too fast a pixel clock can slow the rest of the simulation.

Table 3-392 Ports

Name Protocol Type Description
clk_in ClockSignal Slave Master clock input, typically 24MHz, to drive pixel clock timing.
display LCD Master Connection to visualization component.
intr Signal Master Interrupt signaling line for flyback events.
pvbus PVBus Slave Slave port for connection to PV bus master/decoder.
pvbus_m PVBus Master DMA port for collecting video data from memory/framebuffer.

Table 3-393 Parameters for PL370_HDLCD

Name Type Default value Description
diagnostics int 0x0 Diagnostics level
disable_snooping_dma bool 0x0 Disable DMA snooping
force_frame_rate int 0x32 Force frame rate to the value of the parameter in frames per simulated second, regardless of the input clock. When 0, use the input clock as a pixel clock
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