3.4.12 ARMCortexA57x1CT

ARMCortexA57x1CT CPU component. This model is written in C++ and models version r0p0 of the RTL.

The number of cores that are included in the component (1-4) is given by the component name. The per-core parameters are preceded by cpun, where n identifies the core (0-3).

Differences between the CT model and RTL implementations

This component has the following differences from the corresponding revision of the RTL implementation:

  • The value of the AArch64 PMCEID0_EL0 register, and the AArch32 alias of this register, differs in the model from the TRM value. The model value reflects the model counters.
  • The mechanisms for setting the affinity fields of the MPIDR. The RTL has two ports:
    • CLUSTERIDAFF1[7:0].
    • CLUSTERIDAFF2[7:0].
    AFF1 sets the value of MPIDR bits[15:8] and AFF2 sets the value of MPIDR bits[23:16]. In contrast, the model has a single CLUSTER_ID port. This difference allows the setting of bits[23:8] of the MPIDR using bits[15:0] of the CLUSTER_ID value.
  • The memory mapped debug registers have a view for cores and a view for external debug agents. In the model, these views require two PVBus ports. In hardware, the system designer decides how the implementation differentiates the views.
  • In the model, a single peer event port combines the functionality of the eventi and evento signals in the RTL.
  • The Generic Timers are Programmer’s View (PV) level abstractions: a model-specific protocol connects the cntvalueb port to the MemoryMappedCounterModule.
  • The GIC CPU Interface is a PV level abstraction: a model-specific protocol connects the GIC CPU Interface to the GIC Distributor.
  • The CoreSight™ Cross Trigger Interface (CTI) is a PV level abstraction: the interface is a model-specific one.
  • The model has no mechanism to read the internal memory that the Cache and TLB structures use, through the implementation defined region of the system coprocessor interface. This memory includes the RAM Index Register, IL1DATA Registers, DL1DATA Registers, and associated functionality.
  • The model does not implement:
    • ETM registers.
    • The PMUEVENT bus.
    • The WARMRESETREQ signal. However, the warm reset code sequence (see the section Code sequence to request a Warm reset as a result of RMR_ELx.RR in the Arm®v8‑A Architecture Reference Manual) makes the model simulate a warm reset of the core.
    • The PMUSNAPSHOTREQ and PMUSNAPSHOTACK signals.
    • The EXTERRIRQ and INTERRIRQ signals.
    • Processor dynamic-retention signals.
    • The SYSBARDISABLE signal.
    • The DBGPWRDUP, DBGPWRUPREQ, DBGNOPWRDWN, and DBGRSTREQ debug power management signals.

Debug features

All modeled registers are visible in the debugger.

This component directly supports single-address unconditional instruction breakpoints, unconditional instruction address range breakpoints, and single-address unconditional data breakpoints. The debugger might augment these with more complex combinations of breakpoints.

The model does not support CADI exception breakpoints. Instead, it implements exception breakpoints as register breakpoints on pseudoregisters, named after the exceptions, in the Vectors register group.

This component presents virtual and physical views of memory. The virtual views are:

  • Secure Monitor.
  • NS Hyp.
  • Guest.

These views are 264 bytes in size.

The physical views are:

  • Physical Memory (Secure).
  • Physical Memory (Non-secure).

These views are 264 bytes in size, however the maximum physical address permissible by the Cortex®‑A57 processor is 244 - 1.

Additional ports and parameter information

  • The cache latency parameters are only effective when you enable cache-state modeling.
  • Timing annotation for transactions downstream of the cache and TLB models propagates through the models.
cryptodisable[4]
ARMv8 Cryptography Extensions require a separate package, which is subject to export license conditions. Contact ARM for details.
dev_debug_s, memorymapped_debug_s
The system designer decides whether a debug APB ties the external debug view with other system views. In the model, use a PVBusDecoder to direct traffic to the correct port.

Table 3-98 Ports

Name Protocol Type Description
CNTHPIRQ[4] 2.7.2 Signal protocol Master The per-EL counter signal.
CNTPNSIRQ[4] 2.7.2 Signal protocol Master The per-EL counter signal.
CNTPSIRQ[4] 2.7.2 Signal protocol Master The per-EL counter signal.
CNTVIRQ[4] 2.7.2 Signal protocol Master The per-EL counter signal.
aa64naa32[4] 2.7.2 Signal protocol Slave Register width after reset.
acp_s PVBus Slave AXI ACP slave port.
broadcastcachemaint 2.7.2 Signal protocol Slave Enable broadcasting of cache maintenance operations to downstream caches.
broadcastinner 2.7.2 Signal protocol Slave Enable broadcasting of Inner Shareable transactions.
broadcastouter 2.7.2 Signal protocol Slave Enable broadcasting of Outer Shareable transactions.
cfgend[4] 2.7.2 Signal protocol Slave This signal if for EE bit initialisation.
cfgsdisable 2.7.2 Signal protocol Slave This signal disables write access to some secure Interrupt Controller registers.
cfgte[4] 2.7.2 Signal protocol Slave This signal provides default exception handling state.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
clrexmonack 2.7.2 Signal protocol Master Acknowledge handshake signal for the clrexmonreq signal
clrexmonreq 2.7.2 Signal protocol Slave Signals the clearing of an external global exclusive monitor
clusterid 2.7.4 Value protocol Slave The port reads the value in CPU ID register field, bits[11:8] of the MPIDR.
cntvalueb 2.6.1 CounterInterface protocol Slave Interface to SoC level counter module.
commirq[4] 2.7.2 Signal protocol Master Interrupt signal from debug communications channel.
commrx[4] 2.7.2 Signal protocol Master Receive portion of Data Transfer Register full.
commtx[4] 2.7.2 Signal protocol Master Transmit portion of Data Transfer Register empty.
cp15sdisable[4] 2.7.2 Signal protocol Slave This signal disables write access to some system control processor registers.
cpuporeset[4] 2.7.2 Signal protocol Slave Power on reset. Initializes all the processor logic, including debug logic.
cryptodisable[4] 2.7.2 Signal protocol Slave Disable cryptography extensions after reset.
cti[4] 2.6.4 v8EmbeddedCrossTrigger_controlprotocol protocol Master Cross trigger matrix port.
ctidbgirq[4] 2.7.2 Signal protocol Master Cross Trigger Interface (CTI) interrupt trigger output.
dbgack[4] 2.7.2 Signal protocol Master External debug interface.
dbgen[4] 2.7.2 Signal protocol Slave External debug interface.
dbgnopwrdwn[4] 2.7.2 Signal protocol Master These signals relate to core power down.
dbgpwrupreq[4] 2.7.2 Signal protocol Master These signals relate to core power down.
dev_debug_s PVBus Slave External debug interface.
edbgrq[4] 2.7.2 Signal protocol Slave External debug interface.
event 2.7.2 Signal protocol Peer This peer port of event input (and output) is for wakeup from WFE.
fiq[4] 2.7.2 Signal protocol Slave This signal drives the CPUs fast-interrupt handling.
gicv3_redistributor_s[4] 2.6.2 GICv3Comms protocol Slave GICv3 AXI-stream port.
irq[4] 2.7.2 Signal protocol Slave This signal drives the CPUs interrupt handling.
l2flushdone 2.7.2 Signal protocol Master Flush of L2 memory system complete
l2flushreq 2.7.2 Signal protocol Slave Request flush of L2 memory system.
l2reset 2.7.2 Signal protocol Slave Reset the shared L2 memory system controller.
memorymapped_debug_s PVBus Slave External debug interface.
niden[4] 2.7.2 Signal protocol Slave External debug interface.
periphbase 2.7.5 Value_64 protocol Slave This port sets the base address of private peripheral region.
pmuirq[4] 2.7.2 Signal protocol Master Interrupt signal from performance monitoring unit.
presetdbg 2.7.2 Signal protocol Slave Initialize the shared debug APB, Cross Trigger Interface (CTI), and Cross Trigger Matrix (CTM) logic.
pvbus_m0 PVBus Master The core will generate bus requests on this port.
rei[4] 2.7.2 Signal protocol Slave Individual processor RAM Error Interrupt signal input.
reset[4] 2.7.2 Signal protocol Slave Raising this signal will put the core into reset mode.
romaddr 2.7.5 Value_64 protocol Slave Debug ROM base address.
romaddrv 2.7.2 Signal protocol Slave Debug ROM base address valid.
rvbaraddr[4] 2.7.5 Value_64 protocol Slave Reset vector base address.
sei[4] 2.7.2 Signal protocol Slave Per core System Error physical pins.
smpen[4] 2.7.2 Signal protocol Master This signals AMP or SMP mode for each core.
spiden[4] 2.7.2 Signal protocol Slave External debug interface.
spniden[4] 2.7.2 Signal protocol Slave External debug interface.
standbywfe[4] 2.7.2 Signal protocol Master This signal indicates if a core is in WFE state.
standbywfi[4] 2.7.2 Signal protocol Master This signal indicates if a core is in WFI state.
standbywfil2 2.7.2 Signal protocol Master Indicate that all the individual processors and the L2 systems are in a WFI state.
ticks[4] 2.6.3 InstructionCount protocol Master This port should be connected to one of the two ticks ports on a 'visualisation' component, in order to display a running instruction count.
vcpumntirq[4] 2.7.2 Signal protocol Master Interrupt signal for virtual CPU maintenance IRQ.
vfiq[4] 2.7.2 Signal protocol Slave Virtual FIQ.
vinithi[4] 2.7.2 Signal protocol Slave This signal controls of the location of the exception vectors at reset.
virq[4] 2.7.2 Signal protocol Slave Virtual IRQ.
virtio_s PVBus Slave The virtio coherent port, hooks directly into the L2 system and becomes coherent (assuming attributes are set correctly).
vsei[4] 2.7.2 Signal protocol Slave Processor Virtual System Error Interrupt request.

Table 3-99 Parameters for ARM_Cortex-A57

Name Type Default value Description
cpu0.AA64nAA32 bool 0x1 Register width configuration at reset. 0, AArch32. 1, AArch64.
cpu0.CFGEND bool 0x0 Endianness configuration at reset. 0, little endian. 1, big endian.
cpu0.CFGTE bool 0x0 Instruction set state when resetting into AArch32. 0, A32. 1, T32.
cpu0.CP15SDISABLE bool 0x0 Initialize to disable access to some CP15 registers
cpu0.CRYPTODISABLE bool 0x0 Disable cryptographic features.
cpu0.RVBARADDR int 0x0 Value of RVBAR_ELx register.
cpu0.VINITHI bool 0x0 Reset value of SCTLR.V.
cpu0.enable_trace_special_hlt_imm16 bool 0x0 Enable usage of parameter trace_special_hlt_imm16
cpu0.max_code_cache_mb int 0x100 Maximum size of the simulation code cache (MiB). For platforms with more than 2 cores this limit will be scaled down. (e.g 1/8 for 16 or more cores)
cpu0.min_sync_level int 0x0 Force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
cpu0.semihosting-A32_HLT int 0xf000 A32 HLT number for semihosting calls.
cpu0.semihosting-A64_HLT int 0xf000 A64 HLT number for semihosting calls.
cpu0.semihosting-ARM_SVC int 0x123456 A32 SVC number for semihosting calls.
cpu0.semihosting-T32_HLT int 0x3c T32 HLT number for semihosting calls.
cpu0.semihosting-Thumb_SVC int 0xab T32 SVC number for semihosting calls.
cpu0.semihosting-cmd_line string "" Command line available to semihosting calls.
cpu0.semihosting-cwd string "" Base directory for semihosting file access.
cpu0.semihosting-enable bool 0x1 Enable semihosting SVC/HLT traps.
cpu0.semihosting-heap_base int 0x0 Virtual address of heap base.
cpu0.semihosting-heap_limit int 0xf000000 Virtual address of top of heap.
cpu0.semihosting-stack_base int 0x10000000 Virtual address of base of descending stack.
cpu0.semihosting-stack_limit int 0xf000000 Virtual address of stack limit.
cpu0.trace_special_hlt_imm16 int 0xf000 For this HLT number, IF enable_trace_special_hlt_imm16=true, skip performing usual HLT execution but call MTI trace if registered
cpu0.vfp-enable_at_reset bool 0x0 Enable VFP in CPACR, CPPWR, NSACR at reset. Warning: Arm recommends going through the implementation's suggested VFP power-up sequence!

Table 3-100 Parameters for Cluster_ARM_Cortex-A57

Name Type Default value Description
BROADCASTCACHEMAINT bool 0x1 Enable broadcasting of cache maintenance operations to downstream caches. The broadcastcachemaint signal will override this value if used.
BROADCASTINNER bool 0x1 Enable broadcasting of Inner Shareable transactions. The broadcastinner signal will override this value if used.
BROADCASTOUTER bool 0x1 Enable broadcasting of Outer Shareable transactions. The broadcastouter signal will override this value if used.
CLUSTER_ID int 0x0 Processor cluster ID value
DBGROMADDR int 0x0 Initialization value of DBGDRAR register. Bits[47:12] of this register specify the ROM table physical address.
DBGROMADDRV bool 0x0 If true, set bits[1:0] of the CP15 DBGDRAR to indicate that the address is valid
GICDISABLE bool 0x1 Disable the new style GICv3 CPU interface in each core model. Should be left enabled unless the platform contains a GICv3 distributor.
PERIPHBASE int 0x13080000 Base address of peripheral memory space
bus_type int 0x0 Cosmetic change that changes reset value of L2ACTLR register. 0, ACE. 1, CHI. 2, AXI
cpi_div int 0x1 Divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 Multiplier for calculating CPI (Cycles Per Instruction)
dcache-hit_latency int 0x0 L1 D-Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when dcache-state_modelled=true.
dcache-maintenance_latency int 0x0 L1 D-Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when dcache-state_modelled=true.
dcache-miss_latency int 0x0 L1 D-Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when dcache-state_modelled=true.
dcache-prefetch_enabled bool 0x0 Enable simulation of data cache prefetching. This is only used when dcache-state_modelled=true
dcache-read_access_latency int 0x0 L1 D-Cache timing annotation latency for read accesses given in ticks per access (of size dcache-read_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if dcache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, this is only used when dcache-state_modelled=true.
dcache-read_latency int 0x0 L1 D-Cache timing annotation latency for read accesses given in ticks per byte accessed.dcache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when dcache-state_modelled=true.
dcache-snoop_data_transfer_latency int 0x0 L1 D-Cache timing annotation latency for received snoop accesses that perform a data transfer given in ticks per byte accessed. This is only used when dcache-state_modelled=true.
dcache-state_modelled bool 0x0 Set whether D-cache has stateful implementation
dcache-write_access_latency int 0x0 L1 D-Cache timing annotation latency for write accesses given in ticks per access (of size dcache-write_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if dcache-write_latency is set. This is only used when dcache-state_modelled=true.
dcache-write_latency int 0x0 L1 D-Cache timing annotation latency for write accesses given in ticks per byte accessed. dcache-write_access_latency must be set to 0 for per-byte latencies to be applied. This is only used when dcache-state_modelled=true.
enable_simulation_performance_optimizations bool 0x1 With this option enabled, the model will run more quickly, but be less accurate to exact CPU behavior. The model will still be functionally accurate for software, but may increase differences seen between hardware behavior and model behavior for certain workloads (it changes the micro-architectural value of stage12_tlb_size parameter to 1024).
icache-hit_latency int 0x0 L1 I-Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when icache-state_modelled=true.
icache-maintenance_latency int 0x0 L1 I-Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when icache-state_modelled=true.
icache-miss_latency int 0x0 L1 I-Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when icache-state_modelled=true.
icache-prefetch_enabled bool 0x0 Enable simulation of instruction cache prefetching. This is only used when icache-state_modelled=true.
icache-read_access_latency int 0x0 L1 I-Cache timing annotation latency for read accesses given in ticks per access (of size icache-read_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if icache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, this is only used when icache-state_modelled=true.
icache-read_latency int 0x0 L1 I-Cache timing annotation latency for read accesses given in ticks per byte accessed.icache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when icache-state_modelled=true.
icache-state_modelled bool 0x0 Set whether I-cache has stateful implementation
l2cache-hit_latency int 0x0 L2 Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when l2cache-state_modelled=true.
l2cache-maintenance_latency int 0x0 L2 Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when dcache-state_modelled=true.
l2cache-miss_latency int 0x0 L2 Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when l2cache-state_modelled=true.
l2cache-read_access_latency int 0x0 L2 Cache timing annotation latency for read accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l2cache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, this is only used when l2cache-state_modelled=true.
l2cache-read_latency int 0x0 L2 Cache timing annotation latency for read accesses given in ticks per byte accessed.l2cache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when l2cache-state_modelled=true.
l2cache-size int 0x80000 L2 Cache size in bytes.
l2cache-snoop_data_transfer_latency int 0x0 L2 Cache timing annotation latency for received snoop accesses that perform a data transfer given in ticks per byte accessed. This is only used when dcache-state_modelled=true.
l2cache-snoop_issue_latency int 0x0 L2 Cache timing annotation latency for snoop accesses issued by this cache in total ticks. This is only used when dcache-state_modelled=true.
l2cache-write_access_latency int 0x0 L2 Cache timing annotation latency for write accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l2cache-write_latency is set. This is only used when l2cache-state_modelled=true.
l2cache-write_latency int 0x0 L2 Cache timing annotation latency for write accesses given in ticks per byte accessed. l2cache-write_access_latency must be set to 0 for per-byte latencies to be applied. This is only used when l2cache-state_modelled=true.
ptw_latency int 0x0 Page table walker latency for TA (Timing Annotation), expressed in simulation ticks
tlb_latency int 0x0 TLB latency for TA (Timing Annotation), expressed in simulation ticks
walk_cache_latency int 0x0 Walk cache latency for TA (Timing Annotation), expressed in simulation ticks
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