3.7.4 DMC620

ARM Dynamic Memory Controller(DMC620). This model is written in C++.

DMC620 contains the following CADI targets:

  • DMC620

DMC620 contains the following MTI components:

Limitations of the model

  • The model does not support address striping.
  • The model works with linear addresses and not in rank,bank,row,column form.
  • The model includes error injection and detection mechanisms and syndrome registers support only for RAS error types 4 (ECC single-bit SRAM error) and 5 (ECC double-bit SRAM error).
  • Scrubbing functionality is not provided.
  • The model does not implement direct read or write commands.
  • The model does not implement any performance counters.

Differences between the model and hardware

The DMC520 and DMC620 models have different interfaces to those in the hardware due to the level of abstraction of memory in Fast Models. These are the differences:

  • Like the hardware, the model has a slave port for configuring register accesses, apb_pvbus_s, and an AXI interface for incoming memory transactions that are attempting to access memory that is managed by the DMC.

  • The hardware component translates incoming transactions on the AXI interface to a format that is conducive to accessing DRAM chips. The model performs TrustZone® access control and models the DMC readiness state, but does not translate the transactions. If allowed, the model forwards incoming transactions to be handled by a memory storage handling component that works at the transaction level.

Table 3-197 Ports

Name Protocol Type Description
all_or_interrupt_signal 2.7.2 Signal protocol Master A combined interrupt that is the logical OR of the other interrupts.
apb_pvbus_s PVBus Slave Programmers interface to program and control the DMC-620.
arch_fsm_interrupt_signal 2.7.2 Signal protocol Master The DMC has detected a change in the architectural state.
failed_access_interrupt_signal 2.7.2 Signal protocol Master The DMC has detected a system request that has failed a permissions check and a previously detected assertion was not cleared.
filter_pvbus_m PVBus Master DMC master port to memory.
filter_pvbus_s PVBus Slave System interface.
interrupt_cfh_master 2.7.2 Signal protocol Master The DMC has detected and corrected a single bit error on the RAM access.
interrupt_combined_oflow_master 2.7.2 Signal protocol Master The DMC has detected a counter overflow.
interrupt_fh_master 2.7.2 Signal protocol Master The DMC has detected a double bit error on the RAM access.
reset_signal 2.7.2 Signal protocol Slave DMC reset.
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