3.9.16 GIC500

GIC500 Component for distribution of interrupts. This model is written in C++.

GIC500 - about

This is a single-component implementation of the GICv3 architecture with support for 256 cores. You can configure the model to support a maximum of 32 clusters with eight cores per cluster. Use it with an ARMv8-A core to deliver interrupts. It supports a single Interrupt Translation Service for message-based interrupts. It supports the architectural features, but does not support the implementation defined features.

You must configure some parameters in order to use the GIC500 component. For example:

    gic500: GIC500(
        "num_clusters" = 2, 
        "cpus_per_cluster_0" = 4, 
        "cpus_per_cluster_1" = 4, 
        "reg-base" = 0x2c200000, 
        "SPI-count" = 256 
    );

Table 3-289 Ports

Name Protocol Type Description
cfgsdisable 2.7.2 Signal protocol Slave Disable some SPIs signal.
cpu_active_0[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 0.
cpu_active_1[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 1.
cpu_active_10[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 10.
cpu_active_11[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 11.
cpu_active_12[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 12.
cpu_active_13[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 13.
cpu_active_14[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 14.
cpu_active_15[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 15.
cpu_active_16[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 16.
cpu_active_17[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 17.
cpu_active_18[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 18.
cpu_active_19[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 19.
cpu_active_2[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 2.
cpu_active_20[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 20.
cpu_active_21[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 21.
cpu_active_22[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 22.
cpu_active_23[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 23.
cpu_active_24[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 24.
cpu_active_25[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 25.
cpu_active_26[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 26.
cpu_active_27[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 27.
cpu_active_28[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 28.
cpu_active_29[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 29.
cpu_active_3[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 3.
cpu_active_30[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 30.
cpu_active_31[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 31.
cpu_active_4[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 4.
cpu_active_5[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 5.
cpu_active_6[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 6.
cpu_active_7[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 7.
cpu_active_8[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 8.
cpu_active_9[8] 2.7.2 Signal protocol Slave cpu_active pins of cluster 9.
po_reset 2.7.2 Signal protocol Slave Power on reset.
ppix_in_n[8] Signal Slave Private peripheral interrupts of cluster n. 0 <= n <= 31. 16 <= x <= 31.
pvbus_m PVBus Master Memory bus out: transactions generated by the IRI.
pvbus_s PVBus Slave Memory bus in: memory-mapped register accesses are accepted on this interface.
redistributor_m[256] 2.6.2 GICv3Comms protocol Master Input from and output to CPU interface.
reset 2.7.2 Signal protocol Slave Reset.
spi_in[988] 2.7.2 Signal protocol Slave Shared peripheral interrupts.
wake_request_0[8] 2.7.2 Signal protocol Master Power management outputs of cluster 0.
wake_request_1[8] 2.7.2 Signal protocol Master Power management outputs of cluster 1.
wake_request_10[8] 2.7.2 Signal protocol Master Power management outputs of cluster 10.
wake_request_11[8] 2.7.2 Signal protocol Master Power management outputs of cluster 11.
wake_request_12[8] 2.7.2 Signal protocol Master Power management outputs of cluster 12.
wake_request_13[8] 2.7.2 Signal protocol Master Power management outputs of cluster 13.
wake_request_14[8] 2.7.2 Signal protocol Master Power management outputs of cluster 14.
wake_request_15[8] 2.7.2 Signal protocol Master Power management outputs of cluster 15.
wake_request_16[8] 2.7.2 Signal protocol Master Power management outputs of cluster 16.
wake_request_17[8] 2.7.2 Signal protocol Master Power management outputs of cluster 17.
wake_request_18[8] 2.7.2 Signal protocol Master Power management outputs of cluster 18.
wake_request_19[8] 2.7.2 Signal protocol Master Power management outputs of cluster 19.
wake_request_2[8] 2.7.2 Signal protocol Master Power management outputs of cluster 2.
wake_request_20[8] 2.7.2 Signal protocol Master Power management outputs of cluster 20.
wake_request_21[8] 2.7.2 Signal protocol Master Power management outputs of cluster 21.
wake_request_22[8] 2.7.2 Signal protocol Master Power management outputs of cluster 22.
wake_request_23[8] 2.7.2 Signal protocol Master Power management outputs of cluster 23.
wake_request_24[8] 2.7.2 Signal protocol Master Power management outputs of cluster 24.
wake_request_25[8] 2.7.2 Signal protocol Master Power management outputs of cluster 25.
wake_request_26[8] 2.7.2 Signal protocol Master Power management outputs of cluster 26.
wake_request_27[8] 2.7.2 Signal protocol Master Power management outputs of cluster 27.
wake_request_28[8] 2.7.2 Signal protocol Master Power management outputs of cluster 28.
wake_request_29[8] 2.7.2 Signal protocol Master Power management outputs of cluster 29.
wake_request_3[8] 2.7.2 Signal protocol Master Power management outputs of cluster 3.
wake_request_30[8] 2.7.2 Signal protocol Master Power management outputs of cluster 30.
wake_request_31[8] 2.7.2 Signal protocol Master Power management outputs of cluster 31.
wake_request_4[8] 2.7.2 Signal protocol Master Power management outputs of cluster 4.
wake_request_5[8] 2.7.2 Signal protocol Master Power management outputs of cluster 5.
wake_request_6[8] 2.7.2 Signal protocol Master Power management outputs of cluster 6.
wake_request_7[8] 2.7.2 Signal protocol Master Power management outputs of cluster 7.
wake_request_8[8] 2.7.2 Signal protocol Master Power management outputs of cluster 8.
wake_request_9[8] 2.7.2 Signal protocol Master Power management outputs of cluster 9.

Table 3-290 Parameters for GIC500

Name Type Default value Description
GICD_ITARGETSR-RAZWI bool 0x0 If true, the GICD_ITARGETS registers are RAZ/WI
ITS-count int 0x1 Number of Interrupt Translation Services to be instantiated (0=none)
ITS-device-bits int 0x10 Number of bits supported for ITS device IDs.
ITS-threaded-command-queue bool 0x1 Enable execution of ITS commands in a separate thread which is sometimes required for cosimulation
SPI-count int 0xe0 Number of SPIs that are implemented.
cpus_per_cluster_0 int 0x1 Number of cores within cluster 0
cpus_per_cluster_1 int 0x1 Number of cores within cluster 1
cpus_per_cluster_10 int 0x1 Number of cores within cluster 10
cpus_per_cluster_11 int 0x1 Number of cores within cluster 11
cpus_per_cluster_12 int 0x1 Number of cores within cluster 12
cpus_per_cluster_13 int 0x1 Number of cores within cluster 13
cpus_per_cluster_14 int 0x1 Number of cores within cluster 14
cpus_per_cluster_15 int 0x1 Number of cores within cluster 15
cpus_per_cluster_16 int 0x1 Number of cores within cluster 16
cpus_per_cluster_17 int 0x1 Number of cores within cluster 17
cpus_per_cluster_18 int 0x1 Number of cores within cluster 18
cpus_per_cluster_19 int 0x1 Number of cores within cluster 19
cpus_per_cluster_2 int 0x1 Number of cores within cluster 2
cpus_per_cluster_20 int 0x1 Number of cores within cluster 20
cpus_per_cluster_21 int 0x1 Number of cores within cluster 21
cpus_per_cluster_22 int 0x1 Number of cores within cluster 22
cpus_per_cluster_23 int 0x1 Number of cores within cluster 23
cpus_per_cluster_24 int 0x1 Number of cores within cluster 24
cpus_per_cluster_25 int 0x1 Number of cores within cluster 25
cpus_per_cluster_26 int 0x1 Number of cores within cluster 26
cpus_per_cluster_27 int 0x1 Number of cores within cluster 27
cpus_per_cluster_28 int 0x1 Number of cores within cluster 28
cpus_per_cluster_29 int 0x1 Number of cores within cluster 29
cpus_per_cluster_3 int 0x1 Number of cores within cluster 3
cpus_per_cluster_30 int 0x1 Number of cores within cluster 30
cpus_per_cluster_31 int 0x1 Number of cores within cluster 31
cpus_per_cluster_4 int 0x1 Number of cores within cluster 4
cpus_per_cluster_5 int 0x1 Number of cores within cluster 5
cpus_per_cluster_6 int 0x1 Number of cores within cluster 6
cpus_per_cluster_7 int 0x1 Number of cores within cluster 7
cpus_per_cluster_8 int 0x1 Number of cores within cluster 8
cpus_per_cluster_9 int 0x1 Number of cores within cluster 9
delay-ITS-accesses bool 0x1 Delay accesses from the ITS until GICR_SYNCR is read.
delay-redistributor-accesses bool 0x1 Delay memory accesses from the redistributor until GICR_SYNCR is read.
enable_protocol_checking bool 0x0 Enable/disable protocol checking at cpu interface
enabled bool 0x1 Enable GICv3 functionality; when false the component is inactive.
has-two-security-states bool 0x1 If true, has two security states
num_clusters int 0x1 Number of implemented affinity level1 clusters
print-memory-map bool 0x0 Print memory map to stdout
redistributor-threaded-sync bool 0x1 Enable execution of redistributor delayed transactions in a separate thread which is sometimes required for cosimulation
reg-base int 0x2c010000 GIC500 base address
using-generated-memorymap bool 0x1 Use the generated memorymap for the GIC500 and warn if superfluous parameters are passed
wakeup-on-reset bool 0x0 Go against specification and start redistributors in woken-up state at reset. This allows software that was written for previous versions of the GICv3 specification to work correctly. This should not be used for production code or when the distributor is used separately from the core fast model.
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