3.7.7 DualClusterSystemConfigurationBlock

Dual Cluster System Configuration Block. This model is written in LISA+.

DualClusterSystemConfigurationBlock contains the following CADI targets:

  • DualClusterSystemConfigurationBlock

DualClusterSystemConfigurationBlock contains the following MTI components:

Table 3-200 Ports

Name Protocol Type Description
clk_in ClockSignal Slave -
cluster0_cfgend[4] 2.7.2 Signal protocol Master -
cluster0_cfgte[4] 2.7.2 Signal protocol Master -
cluster0_clusterid 2.7.4 Value protocol Master -
cluster0_corereset[4] 2.7.2 Signal protocol Master -
cluster0_cpuporeset[4] 2.7.2 Signal protocol Master -
cluster0_cxreset[4] 2.7.2 Signal protocol Master -
cluster0_eventi 2.7.2 Signal protocol Peer -
cluster0_evento 2.7.2 Signal protocol Peer -
cluster0_iminlen 2.7.2 Signal protocol Master -
cluster0_l2reset 2.7.2 Signal protocol Master -
cluster0_standbywfi[4] 2.7.2 Signal protocol Slave -
cluster0_vinithi[4] 2.7.2 Signal protocol Master -
cluster1_cfgend[4] 2.7.2 Signal protocol Master -
cluster1_clusterid 2.7.4 Value protocol Master -
cluster1_corereset[4] 2.7.2 Signal protocol Master -
cluster1_cpuporeset[4] 2.7.2 Signal protocol Master -
cluster1_eventi 2.7.2 Signal protocol Peer -
cluster1_evento 2.7.2 Signal protocol Peer -
cluster1_scureset 2.7.2 Signal protocol Master -
cluster1_standbywfi[4] 2.7.2 Signal protocol Slave -
cluster1_teinit[4] 2.7.2 Signal protocol Master -
cluster1_vinithi[4] 2.7.2 Signal protocol Master -
daughter_leds_state 2.7.6 ValueState protocol Master -
daughter_user_switches 2.7.6 ValueState protocol Master -
intgen[128] 2.7.2 Signal protocol Master -
periphbase 2.7.5 Value_64 protocol Master -
periphbase_32 2.7.4 Value protocol Master -
pvbus PVBus Slave -
system_reset 2.7.2 Signal protocol Master -
vgic_configuration_port v7_VGIC_Configuration_Protocol Master -

Table 3-201 Parameters for DualClusterSystemConfigurationBlock

Name Type Default value Description
CFG_ACTIVECLUSTER int 0x1 Select which cluster will come out of reset coming out of power-on: bit[0] for primary cluster (Cortex-A15), bit[1] for secondary cluster (Cortex-A7). Value 0 is not allowed as it will hold both clusters in reset indefinitely!
Cluster0IdOnPOReset int 0x0 ClusterId for primary cluster (Cortex-A15) on power-on reset
Cluster1IdOnPOReset int 0x1 ClusterId for secondary cluster (Cortex-A7) on power-on reset
DCSCB_PERIPHBASE int 0x1e000000 PERIPHBASE
DCS_AID int 0x0 DCS_AID is the Auxiliary ID Register
DCS_ID int 0x41120000 The value returned by the DCS_ID register.
DCS_ID_BUILD_NUMBER int 0x1 DCS_ID build number
DCS_LEDS int 0x0 DCS_LEDS represents eight LEDs on the board that form an 8-bit value that can be r/w from the Dual Cluster System Configuration Block
DCS_SW int 0x0 DCS_SW represents eight switches on the board that form an 8-bit value that can be read from the Dual Cluster System Configuration Block
FlipVGICWiringForCluster0AndCluster1 bool 0x0 Flip the VGIC wiring round for cluster0 and cluster1. With this false, then cpu0 of cluster0 is cpu interface 0 on the VGIC. If this is true then cpu0 of cluster1 becomes cpu interface 0 on the VGIC.
INTGEN_INTS int 0x3 Number of custom IRQs controlled by interrupt generator is INTGEN_INTS * 32 + 32.
NumberOfCoresInCluster0 int 0x0 The number of cores in the primary cluster
NumberOfCoresInCluster1 int 0x0 The number of cores in the secondary cluster
ResetValueOfDaughterUserSwitches int 0x0 Reset value of the user switches on the daughterboard
stop_on_sequence_id int 0x0 If non-zero the sequence_id of the SW trace mechanism on which to halt the simulator
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