3.9.23 ICS307

Serially Programmable Clock Source. This model is written in LISA+.

ICS307 contains the following CADI targets:

  • ICS307

ICS307 - about

You can use this component to convert the rate of one ClockSignal to another ClockSignal by using configurable multiplier, divider, and scale values. The divider ratio can be set by startup parameters or at runtime by a configuration port. Changes to the input ClockSignal rate and divider ratio are reflected immediately by the output ClockSignal ports.

Three values determine the divisor ratio:

  • vdw.
  • rdw.
  • od.

To calculate the divisor ratio, use:

Divisor = ((rdw+2) * scale) / (2 * (vdw+8))

where scale is derived from this table indexed by od:

Table 3-303 od to scale conversion

od scale
0 10
1 2
2 8
3 4
4 5
5 7
6 3
7 6

The default values of vdw, rdw and od are 4, 6 and 3 to give a default divisor rate of:

((6+2) * 4) / (2 * (4+8)) = 4/3


Arm expects this component to have little effect on the performance of PV systems. However, modifying the ICS307 timing parameters is relatively slow, so ARM recommends you do so rarely.

Table 3-304 Ports

Name Protocol Type Description
clk_in ClockSignal Slave Master clock rate.
clk_out_clk1 ClockSignal Master Modified clock rate.
clk_out_ref ClockSignal Master Pass through of master clock rate for divider chaining.
configuration 2.4.5 ICS307Configuration protocol Slave Configuration port for setting divider ratio dynamically.

Table 3-305 Parameters for ICS307

Name Type Default value Description
od int 0x3 OD
rdr int 0x6 RDR
vdw int 0x4 VDW
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