3.9.19 GIC600_Filter

GIC-600 IRI implementation: Single chip validation/filter component variant limited to 265 PE. This model is written in C++.


GIC600 and GIC600_Filter are minimal models of an ARM GIC-600 Generic Interrupt Controller, suitable for single-chip systems. They provide a simple configuration interface that allows designers to introduce GIC600-like functionality to their systems, while only implementing the architectural behavior, as defined by the GICv3 architecture.

All implementation-specific registers and functionality are unimplemented except for GICR_PWRR, for which an effectless but stateful implementation is present. This allows a power-aware software implementation to observe the correct value.

As with the other GIC components, there are two variants of the model with slightly different memory interfaces. Both GIC600 and GIC600_Filter have a pvbus_s port for register accesses and a pvbus_m port for the LPI-related traffic from redistributors and the ITS.

In addition, the GIC600_Filter variant has a pvbus_filtermiss_m port, to which any transaction coming on the pvbus_s port and not directed to a 4K page used by the GIC is forwarded unmodified. Such transactions are terminated in the component when using the GIC600 variant.

It is recommended to use the GIC600 variant in most cases.

Table 3-295 Ports

Name Protocol Type Description
cpu_active_s[256] 2.7.2 Signal protocol Slave CPUActive pins.
po_reset 2.7.2 Signal protocol Slave Reset.
ppi_in_n[16] Signal Slave Private peripheral interrupts (ID16-ID31) for cpu n, where 0 ≤ n ≤ 255.
pvbus_filtermiss_m PVBus Master Memory bus out. Transactions not filtered by the component.
pvbus_m PVBus Master Memory bus out: transactions generated by the IRI.
pvbus_s PVBus Slave Memory bus in: memory-mapped register accesses are accepted on this interface.
redistributor_m[256] 2.6.2 GICv3Comms protocol Master Input from and output to CPU interface.
reset 2.7.2 Signal protocol Slave Reset.
spi_in[960] 2.7.2 Signal protocol Slave Shared peripheral interrupts.
wake_request[256] 2.7.2 Signal protocol Master Power management outputs.

Table 3-296 Parameters for GIC600

Name Type Default value Description
ARE-fixed-to-one bool 0x0 GICv2 compatibility is not supported and GICD_CTLR.ARE_* is always one
CPU-affinities string "" A comma separated list of dotted quads containing the affinities of all PEs connected to this IRI.
DS-behaviour int 0x2 GICD_CTLR.DS field behaviour: 0:RAZ/WI, 1:RAO/WI, 2:RW
ITS-ID-bits int 0x10 Number of interrupt bits supported by ITS.
ITS-collection-ID-bits int 0x8 Number of collection bits supported by ITS (optional parameter, 0 => 16bits support and GITS_TYPER.CIL=0
ITS-count int 0x1 Number of Interrupt Translation Services to be instantiated (0=none)
ITS-device-bits int 0x10 Number of bits supported for ITS device IDs.
PPI-count int 0x10 Selects the number of PPI available for each PE as 8( id22-27,29,30), 12(id 20-31) or 16(id 16-31)
SPI-blocks int 0x1e Number of SPI blocks supported by the IRI, each block contains 32 SPIs
affinity-width string "" A dotted quad indicating the bitwidth of fields at each affinity level
chip-select-affinity-level int 0x3 Affinity level 2 or 3 can be used for chip select, affinity width is forced to 0 for the level and above as this model supports one chip only
direct-lpi-support bool 0x0 Enable support for LPI operations through GICR registers
enabled bool 0x1 Enable GICv3 functionality; when false the component is inactive.
print-memory-map bool 0x0 Print memory map to stdout
reg-base int 0x2c010000 GIC-600 base address
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