3.9.26 MMU_400

MMU-400 component. This model is written in LISA+.

MMU_400 contains the following CADI targets:

  • MMU_400
  • MMU_400_BASE

MMU_400 contains the following MTI components:

Registers

This component models all architectural registers as the Technical Reference Manual (TRM) specifies, except that it does not model any of the performance registers.

MMU-400 does not have an SMMU_STLBGSTATUS register because the Secure side is a nominal pass-through. MMU-400 only has stage 2 support and you cannot use stage 2 on the Secure side.

The SMMU_NSACR is an alias of the Non-secure SMMU_ACR. This component models SMMU_ACR as RAZ/WI.

The *ACR registers have IMP DEF contents. This component models only the PAGESIZE bit of the SACR, as non-RAZ/WI. It models no other IMP DEF registers.

Performance

This component has little effect on system performance. As for the hardware, TLB misses affect performance. To reduce this, increase the TLB size with the tlb_depth parameter.

Additional parameter information

use_ssd_determination_table
If true, the bottom 16 bits of the MasterID encode the SSD_Index. They must be < 2^ssd_index_width. If false, they encode the SSD state directly (zero is Secure and nonzero is Non-secure).
use_label_mapping
Use true if your upstream devices have labels in the top 16 bits of the transaction MasterID.

Note:

The model does not have a concept of AXI-ID, but a transaction can have a MasterID set on it.
Label your upstream components 0…N so that the parameters of this component can map those integers to StreamID and SSD_Index. Use false if the StreamID is encoded in the top 16 bits of the MasterID and the bottom 16 bits encode either the SSD_Index or the SSD state directly, depending on use_ssd_determination_table. Typically in hardware, a device emits different AXI-IDs, depending on what it is doing. In the model, MasterIDs are usually not diverse and a device might only emit one MasterID.

Table 3-311 Ports

Name Protocol Type Description
apb3_control_ns PVBus Slave APBv3 control port for Non-secure access to the register file. If this port is used do not use the APBv4 port.
apb3_control_s PVBus Slave APBv3 control port for Secure access to the register file. If this port is used do not use the APBv4 port.
apb4_control PVBus Slave APBv4 control port for access to the register file. If this port is used do not use the APBv3 ports.
cfg_cttw_in 2.7.2 Signal protocol Slave Enables coherent page table walks.
cfg_flt_irpt_ns 2.7.2 Signal protocol Master Non-secure configuration access fault interrupt. Corresponds to SMMU architectural signal SMMU_NSgCfgIrpt.
cfg_flt_irpt_s 2.7.2 Signal protocol Master Secure configuration access fault interrupt. Corresponds to SMMU architectural signal SMMU_gCfgIrpt.
comb_irpt_ns 2.7.2 Signal protocol Master Non-secure combined interrupt.
comb_irpt_s 2.7.2 Signal protocol Master Secure combined interrupt.
cxt_irpt_ns 2.7.2 Signal protocol Master Non-secure context bank fault.
glbl_flt_irpt_ns 2.7.2 Signal protocol Master Global Non-secure fault interrupt. Corresponds to SMMU architectural signal SMMU_NSgIrpt.
glbl_flt_irpt_s 2.7.2 Signal protocol Master Global Secure fault interrupt. Corresponds to SMMU architectural signal SMMU_gIrpt.
priv_internals MMU_400_Internals Slave For internal use only, please do not use.
pvbus_m PVBus Master Downstream port of the MMU, where translated transactions emerge.
pvbus_ptw_m PVBus Master Downstream port for page table walks if configured using the ptw_has_separate_port parameter.
pvbus_s PVBus Slave Upstream port of the MMU. Addresses on the port are in VA/IPA.
reset_in 2.7.2 Signal protocol Slave Signal to reset the MMU.

Table 3-312 Parameters for MMU_400

Name Type Default value Description
always_secure_ssd_indices string "" Non-programmable SSD Indexes that are always secure (e.g. 0, 6, 35-64).
cfg_cttw bool 0x1 Perform coherent page table walks
dump_unpredictablity_in_user_flags bool 0x0 Override the user flags to encode unpredictable information (validation only)
label0_read_ssd int 0x0 Label0: Read SDD or SSD_Index
label0_read_stream_id int 0x0 Label0: Read Stream ID
label0_write_ssd int 0x0 Label0: Write SDD or SSD_Index
label0_write_stream_id int 0x0 Label0: Write Stream ID
label10_read_ssd int 0x0 Label10: Read SDD or SSD_Index
label10_read_stream_id int 0x0 Label10: Read Stream ID
label10_write_ssd int 0x0 Label10: Write SDD or SSD_Index
label10_write_stream_id int 0x0 Label10: Write Stream ID
label11_read_ssd int 0x0 Label11: Read SDD or SSD_Index
label11_read_stream_id int 0x0 Label11: Read Stream ID
label11_write_ssd int 0x0 Label11: Write SDD or SSD_Index
label11_write_stream_id int 0x0 Label11: Write Stream ID
label12_read_ssd int 0x0 Label12: Read SDD or SSD_Index
label12_read_stream_id int 0x0 Label12: Read Stream ID
label12_write_ssd int 0x0 Label12: Write SDD or SSD_Index
label12_write_stream_id int 0x0 Label12: Write Stream ID
label13_read_ssd int 0x0 Label13: Read SDD or SSD_Index
label13_read_stream_id int 0x0 Label13: Read Stream ID
label13_write_ssd int 0x0 Label13: Write SDD or SSD_Index
label13_write_stream_id int 0x0 Label13: Write Stream ID
label14_read_ssd int 0x0 Label14: Read SDD or SSD_Index
label14_read_stream_id int 0x0 Label14: Read Stream ID
label14_write_ssd int 0x0 Label14: Write SDD or SSD_Index
label14_write_stream_id int 0x0 Label14: Write Stream ID
label15_read_ssd int 0x0 Label15: Read SDD or SSD_Index
label15_read_stream_id int 0x0 Label15: Read Stream ID
label15_write_ssd int 0x0 Label15: Write SDD or SSD_Index
label15_write_stream_id int 0x0 Label15: Write Stream ID
label16_read_ssd int 0x0 Label16: Read SDD or SSD_Index
label16_read_stream_id int 0x0 Label16: Read Stream ID
label16_write_ssd int 0x0 Label16: Write SDD or SSD_Index
label16_write_stream_id int 0x0 Label16: Write Stream ID
label17_read_ssd int 0x0 Label17: Read SDD or SSD_Index
label17_read_stream_id int 0x0 Label17: Read Stream ID
label17_write_ssd int 0x0 Label17: Write SDD or SSD_Index
label17_write_stream_id int 0x0 Label17: Write Stream ID
label18_read_ssd int 0x0 Label18: Read SDD or SSD_Index
label18_read_stream_id int 0x0 Label18: Read Stream ID
label18_write_ssd int 0x0 Label18: Write SDD or SSD_Index
label18_write_stream_id int 0x0 Label18: Write Stream ID
label19_read_ssd int 0x0 Label19: Read SDD or SSD_Index
label19_read_stream_id int 0x0 Label19: Read Stream ID
label19_write_ssd int 0x0 Label19: Write SDD or SSD_Index
label19_write_stream_id int 0x0 Label19: Write Stream ID
label1_read_ssd int 0x0 Label1: Read SDD or SSD_Index
label1_read_stream_id int 0x0 Label1: Read Stream ID
label1_write_ssd int 0x0 Label1: Write SDD or SSD_Index
label1_write_stream_id int 0x0 Label1: Write Stream ID
label20_read_ssd int 0x0 Label20: Read SDD or SSD_Index
label20_read_stream_id int 0x0 Label20: Read Stream ID
label20_write_ssd int 0x0 Label20: Write SDD or SSD_Index
label20_write_stream_id int 0x0 Label20: Write Stream ID
label21_read_ssd int 0x0 Label21: Read SDD or SSD_Index
label21_read_stream_id int 0x0 Label21: Read Stream ID
label21_write_ssd int 0x0 Label21: Write SDD or SSD_Index
label21_write_stream_id int 0x0 Label21: Write Stream ID
label22_read_ssd int 0x0 Label22: Read SDD or SSD_Index
label22_read_stream_id int 0x0 Label22: Read Stream ID
label22_write_ssd int 0x0 Label22: Write SDD or SSD_Index
label22_write_stream_id int 0x0 Label22: Write Stream ID
label23_read_ssd int 0x0 Label23: Read SDD or SSD_Index
label23_read_stream_id int 0x0 Label23: Read Stream ID
label23_write_ssd int 0x0 Label23: Write SDD or SSD_Index
label23_write_stream_id int 0x0 Label23: Write Stream ID
label24_read_ssd int 0x0 Label24: Read SDD or SSD_Index
label24_read_stream_id int 0x0 Label24: Read Stream ID
label24_write_ssd int 0x0 Label24: Write SDD or SSD_Index
label24_write_stream_id int 0x0 Label24: Write Stream ID
label25_read_ssd int 0x0 Label25: Read SDD or SSD_Index
label25_read_stream_id int 0x0 Label25: Read Stream ID
label25_write_ssd int 0x0 Label25: Write SDD or SSD_Index
label25_write_stream_id int 0x0 Label25: Write Stream ID
label26_read_ssd int 0x0 Label26: Read SDD or SSD_Index
label26_read_stream_id int 0x0 Label26: Read Stream ID
label26_write_ssd int 0x0 Label26: Write SDD or SSD_Index
label26_write_stream_id int 0x0 Label26: Write Stream ID
label27_read_ssd int 0x0 Label27: Read SDD or SSD_Index
label27_read_stream_id int 0x0 Label27: Read Stream ID
label27_write_ssd int 0x0 Label27: Write SDD or SSD_Index
label27_write_stream_id int 0x0 Label27: Write Stream ID
label28_read_ssd int 0x0 Label28: Read SDD or SSD_Index
label28_read_stream_id int 0x0 Label28: Read Stream ID
label28_write_ssd int 0x0 Label28: Write SDD or SSD_Index
label28_write_stream_id int 0x0 Label28: Write Stream ID
label29_read_ssd int 0x0 Label29: Read SDD or SSD_Index
label29_read_stream_id int 0x0 Label29: Read Stream ID
label29_write_ssd int 0x0 Label29: Write SDD or SSD_Index
label29_write_stream_id int 0x0 Label29: Write Stream ID
label2_read_ssd int 0x0 Label2: Read SDD or SSD_Index
label2_read_stream_id int 0x0 Label2: Read Stream ID
label2_write_ssd int 0x0 Label2: Write SDD or SSD_Index
label2_write_stream_id int 0x0 Label2: Write Stream ID
label30_read_ssd int 0x0 Label30: Read SDD or SSD_Index
label30_read_stream_id int 0x0 Label30: Read Stream ID
label30_write_ssd int 0x0 Label30: Write SDD or SSD_Index
label30_write_stream_id int 0x0 Label30: Write Stream ID
label31_read_ssd int 0x0 Label31: Read SDD or SSD_Index
label31_read_stream_id int 0x0 Label31: Read Stream ID
label31_write_ssd int 0x0 Label31: Write SDD or SSD_Index
label31_write_stream_id int 0x0 Label31: Write Stream ID
label3_read_ssd int 0x0 Label3: Read SDD or SSD_Index
label3_read_stream_id int 0x0 Label3: Read Stream ID
label3_write_ssd int 0x0 Label3: Write SDD or SSD_Index
label3_write_stream_id int 0x0 Label3: Write Stream ID
label4_read_ssd int 0x0 Label4: Read SDD or SSD_Index
label4_read_stream_id int 0x0 Label4: Read Stream ID
label4_write_ssd int 0x0 Label4: Write SDD or SSD_Index
label4_write_stream_id int 0x0 Label4: Write Stream ID
label5_read_ssd int 0x0 Label5: Read SDD or SSD_Index
label5_read_stream_id int 0x0 Label5: Read Stream ID
label5_write_ssd int 0x0 Label5: Write SDD or SSD_Index
label5_write_stream_id int 0x0 Label5: Write Stream ID
label6_read_ssd int 0x0 Label6: Read SDD or SSD_Index
label6_read_stream_id int 0x0 Label6: Read Stream ID
label6_write_ssd int 0x0 Label6: Write SDD or SSD_Index
label6_write_stream_id int 0x0 Label6: Write Stream ID
label7_read_ssd int 0x0 Label7: Read SDD or SSD_Index
label7_read_stream_id int 0x0 Label7: Read Stream ID
label7_write_ssd int 0x0 Label7: Write SDD or SSD_Index
label7_write_stream_id int 0x0 Label7: Write Stream ID
label8_read_ssd int 0x0 Label8: Read SDD or SSD_Index
label8_read_stream_id int 0x0 Label8: Read Stream ID
label8_write_ssd int 0x0 Label8: Write SDD or SSD_Index
label8_write_stream_id int 0x0 Label8: Write Stream ID
label9_read_ssd int 0x0 Label9: Read SDD or SSD_Index
label9_read_stream_id int 0x0 Label9: Read Stream ID
label9_write_ssd int 0x0 Label9: Write SDD or SSD_Index
label9_write_stream_id int 0x0 Label9: Write Stream ID
number_of_contexts int 0x8 Number of context banks
number_of_smrs int 0x20 Number of stream match registers.
percent_tlbstatus_commits int 0xa Percentage of times that a poll of TLBSTATUS will commit the TLBI commands
prefetch_only_requests int 0x0 Handle prefetch-only requests by:- 0 -- deny them 1 -- use debug table walks and TLB entries 2 -- treat them as normal transactions (dangerous)
programmable_non_secure_by_default_ssd_indices string "" Programmable SSD Indexes that are by default non-secure (e.g. 0, 6, 35-84).
programmable_secure_by_default_ssd_indices string "" Programmable SSD Indexes that are by default secure (e.g. 0, 6, 35-84).
ptw_has_separate_port bool 0x1 Page Table Walks use pvbus_ptw_m
pvbus_m_is_ace_lite bool 0x1 Is pvbus_m (the downstream port that translated transaction exit) ACE-Lite
pvbus_ptw_m_is_ace_lite bool 0x1 Is pvbus_ptw_m (the downstream port that is used for walks if ptw_has_separate_port is true) ACE-Lite
stream_id_width int 0x6 StreamID bit width
tlb_depth int 0x40 TLB Depth (0 means 10000). The model will perform best with more TLB entries.
use_label_mapping bool 0x1 Use label mapping
use_ssd_determination_table bool 0x1 Use SSD Determination Table

Table 3-313 Parameters for MMU_400_BASE

Name Type Default value Description
mmu.always_secure_ssd_indices string "" Non-programmable SSD Indexes that are always secure (e.g. 0, 6, 35-64).
mmu.cfg_cttw bool 0x1 Perform coherent page table walks
mmu.dump_unpredictablity_in_user_flags bool 0x0 Override the user flags to encode unpredictable information (validation only)
mmu.number_of_contexts int 0x8 Number of context banks
mmu.number_of_smrs int 0x10 Number of stream match registers.
mmu.percent_tlbstatus_commits int 0xa Percentage of times that a poll of TLBSTATUS will commit the TLBI commands
mmu.prefetch_only_requests int 0x0 Handle prefetch-only requests by:- 0 -- deny them 1 -- use debug table walks and TLB entries 2 -- treat them as normal transactions (dangerous)
mmu.programmable_non_secure_by_default_ssd_indices string "" Programmable SSD Indexes that are by default non-secure (e.g. 0, 6, 35-84).
mmu.programmable_secure_by_default_ssd_indices string "" Programmable SSD Indexes that are by default secure (e.g. 0, 6, 35-84).
mmu.ptw_has_separate_port bool 0x1 Page Table Walks use pvbus_ptw_m
mmu.pvbus_m_is_ace_lite bool 0x1 Is pvbus_m (the downstream port that translated transaction exit) ACE-Lite
mmu.pvbus_ptw_m_is_ace_lite bool 0x1 Is pvbus_ptw_m (the downstream port that is used for walks if ptw_has_separate_port is true) ACE-Lite
mmu.seed int 0x12345678 Seed for SMMU
mmu.stream_id_width int 0x6 StreamID bit width
mmu.tlb_depth int 0x40 TLB Depth (0 means 10000). The model will perform best with more TLB entries.
mmu.use_ssd_determination_table bool 0x1 Use SSD Determination Table
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