3.9.44 PL192_VIC

ARM PrimeCell Vectored Interrupt Controller(PL192). This model is written in LISA+.

PL192_VIC contains the following CADI targets:

  • PL192_VIC

PL192_VIC contains the following MTI components:

PL192_VIC - about

This component aggregates interrupts and generates interrupt signals for the ARM processor. When coupled with an ARM processor that provides a VIC port, routing to the appropriate interrupt handler can be optionally performed in hardware, reducing interrupt latency. The PL192_VIC can also be daisy-chained with other PL192 VICs to permit more than 32 interrupts. The VIC supports hardware and software prioritization of interrupts.

Table 3-346 Ports

Name Protocol Type Description
VICIRQACK 2.7.2 Signal protocol Slave Receive acknowledge signal from next level VIC or processor.
VICIRQACKOUT 2.7.2 Signal protocol Master Used to send out acknowledge signals when daisy chained.
VICIntSource[32] 2.7.2 Signal protocol Slave Interrupt source input sources.
VICVECTADDRIN 2.7.6 ValueState protocol Slave Used to receive vector address when daisy chained.
VICVECTADDROUT 2.7.6 ValueState protocol Master Used to send vector address to next level VIC or processor.
nVICFIQ 2.7.2 Signal protocol Master Send out FIQ signal to the next level VIC or CPI.
nVICFIQIN 2.7.2 Signal protocol Slave Used to receive FIQ signal when daisy chained.
nVICIRQ 2.7.2 Signal protocol Master Send out IRQ signal to the next level VIC or procesessor.
nVICIRQIN 2.7.2 Signal protocol Slave Used to receive IRQ signal when daisy chained.
pvbus PVBus Slave Slave port for register access.
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