3.9.57 SP804_Timer

ARM Dual-Timer Module(SP804). This model is written in LISA+.

SP804_Timer contains the following CADI targets:

  • CounterModule
  • SP804_Timer

SP804_Timer contains the following MTI components:

Table 3-369 Ports

Name Protocol Type Description
clock ClockSignal Slave Clock input, typically 1MHz, driving master count rate.
irq_out0 2.7.2 Signal protocol Master Interrupt signaling.
irq_out1 2.7.2 Signal protocol Master Interrupt signaling.
pvbus PVBus Slave Slave port for register access.
timer_en[2] 2.2.2 ClockRateControl protocol Slave Port for changing the rate of timer n.
Non-ConfidentialPDF file icon PDF version100964_1142_00_en
Copyright © 2014–2018 Arm Limited or its affiliates. All rights reserved.