3.5.1 D71

ARM D71 Display Processor. This model is written in C++.

D71 contains the following CADI targets:

  • D71

D71 contains the following MTI components:

Limitations

  • No support for trusted layers.
  • No support for image enhancements.
  • No coprocessor support for HDR processing.
  • No QoS support.
  • The following configuration parameters are not available:
    • CONFIG_MAX_LINE_SIZE
    • CONFIG_DISPLAY_TBU_EN. TBUs are integrated separately using the given ports.
    • CONFIG_AFBC_DMA_EN. The ADU is present. If it is not used, do not program it.

Table 3-170 Ports

Name Protocol Type Description
apb_pvbus_s_adu PVBus Slave Slave port for register access.
apb_pvbus_s_dpu PVBus Slave -
axi_pvbus_adu_m PVBus Master Master AXI port for the AFBC unit
axi_pvbus_lpu_m[2] PVBus Master Master AXI ports for pipelines
display[2] 2.4.7 LCD protocol Master LCD ports for display outputs
irq0_gcu_out 2.7.2 Signal protocol Master Shared interrupt owned by the GCU
irq1_adu_out 2.7.2 Signal protocol Master Interrupt signal for the ADU block
pixelclock_in[2] ClockSignal Slave Pixel clock inputs for the display outputs
pvbus_tbu_m[2] PVBus Master Master ports for connection to TBU (SMMUv3)
pvbus_tbu_s[2] PVBus Slave Slave ports for loopback from TBU (SMMUv3)
reset_signal 2.7.2 Signal protocol Slave Reset signal.
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