3.9.29 MMU_500_BASE

MMU-500 base component. This model is written in LISA+.

MMU_500_BASE contains the following CADI targets:

  • MMU_500_BASE

MMU_500_BASE contains the following MTI components:

Table 3-319 Ports

Name Protocol Type Description
cfg_cttw_in 2.7.2 Signal protocol Slave The SoC supports coherent page walks, this is meant to be sampled at reset. However, in practice the model has to prevent the race condition between cfg_cttw being asserted at the same 'cycle' as negedge reset. Thus we actually only sample the signal on the first transaction to the SMMU or the first transition on this signal after reset. Thus in the model, we require that cfg_cttw be held for at least this period of time.
comb_irpt_ns 2.7.2 Signal protocol Master "Non-secure combined interrupt"
comb_irpt_s 2.7.2 Signal protocol Master "Secure combined interrupt"
cxt_irpt[128] 2.7.2 Signal protocol Master Non-secure context bank fault.
glbl_flt_irpt_ns 2.7.2 Signal protocol Master Global non-secure Fault Interrupt In the SMMU Architecture this is called SMMU_NSgIrpt.
glbl_flt_irpt_s 2.7.2 Signal protocol Master Global secure Fault Interrupt In the SMMU Architecture this is called SMMU_gIrpt.
identify MMU_500_BASE_IDENTIFY Master This port is a special model port that is used to take a transaction and map it to an SSD/SSD_Index and StreamID.
priv_internals MMU_500_Internals Slave For internal use only, please do not use.
pvbus_control_s PVBus Slave The register port of the device is AXI.
pvbus_m[32] PVBus Master This downstream port is where the translated accesses from pvbus_s emerge. See notes for pvbus_s[] as well. If the Page Table Walk (PTW) does not have a separate port then PTW accesses will emerge at port 0 with the same attributes as described in pvbus_ptw_m.
pvbus_ptw_m PVBus Master This downstream port is where page table walk accesses come from. This is only used if configured to use a separate page table walk port. The MMU-500 will only obey DVM messages if configured to use this port. The page walks come out of this port with the following master_id and user_flags. master_id : 0xFFFFffff The user flags : user_flags[7:0] stage 1 context_id (or 0xFF if stage2 only) user_flags[15:8] stage 2 context_id (or 0xFF if stage 1 with stage 2 bypass) user_flags[18:16] stage 1 level user_flags[21:19] stage 2 level user_flags[31,30] adomain of the transaction NOTE that if the walk is being done for a stage 1 page walk descriptor fetch then the stage 1 level field will indicate that level. If the walk is being done for a stage 2 descriptor fetch, then the stage 2 level field will show that level. If the context-id for a stage is not valid (0xFF) then the 'level' information is 0x7.
pvbus_s[32] PVBus Slave This port is the upstream port of the device, addresses on the port are in the VA/IPA Each TBU in the design is represented by a pair of pvbus_s[tbu_id] and pvbus_m[tbu_id]. That is transactions that go into pvbus_s[tbu_id] will emerge at pvbus_m[tbu_id]. The port index that a transaction comes in on is the tbu_number_ parameter to the MMU_500_BASE_IDENTIFY::identify() function. The identify() function must use all the information it is given by the parameters to map to the architectural concepts of StreamID and SSD_Index/SSD. How it does this is IMPLEMENTATION DEFINED and depends on the topology of the SoC and the masters upstream of the TBUs.
reset_in 2.7.2 Signal protocol Slave The reset pin.

Table 3-320 Parameters for MMU_500_BASE

Name Type Default value Description
mmu.PRIVATE_PARAMETER_personality string "" The personality to use (affects ID codes and various imp def features).
mmu.PRIVATE_PARAMETER_seed int 0x12345678 Seed for randomised SMMU implementation defined behaviour
mmu.PRIVATE_PARAMETER_validation_mode int 0x0 Internal validation mode.
mmu.always_secure_ssd_indices string "" Non-programmable SSD Indexes that are always secure (e.g. 0, 6, 35-64).
mmu.cfg_cttw bool 0x1 Perform coherent page table walks
mmu.dump_unpredictablity_in_user_flags bool 0x0 Override the user flags to encode unpredictable information (validation only)
mmu.number_of_contexts int 0x8 Number of context banks
mmu.number_of_smrs int 0x10 Number of stream match registers.
mmu.percent_tlbstatus_commits int 0xa Percentage of times that a poll of TLBSTATUS will commit the TLBI commands
mmu.prefetch_only_requests int 0x0 Handle prefetch-only requests by:- 0 -- deny them 1 -- use debug table walks and TLB entries 2 -- treat them as normal transactions (dangerous)
mmu.programmable_non_secure_by_default_ssd_indices string "" Programmable SSD Indexes that are by default non-secure (e.g. 0, 6, 35-84).
mmu.programmable_secure_by_default_ssd_indices string "" Programmable SSD Indexes that are by default secure (e.g. 0, 6, 35-84).
mmu.ptw_has_separate_port bool 0x1 Page Table Walks use pvbus_ptw_m (or uses pvbus_m[0])
mmu.supports_nested_translations bool 0x1 Supports nested translations (stage 1 + stage 2)
mmu.tlb_depth int 0x800 TLB Depth (0 means 10000). The model will perform best with more TLB entries.
mmu.use_ssd_determination_table bool 0x1 Use SSD Determination Table
mmu.version string "EAC" Version of the RTL that the model represents. Valid values are LACr1 and EAC.
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