3.4.30 ARMCortexM7CT

ARMCortexM7CT CPU component. This model is written in C++ and models version r0p2 of the RTL.

ARMCortexM7CT contains the following CADI targets:

  • ARM_Cortex-M7

ARMCortexM7CT contains the following MTI components:

Implementation of ITM in M-class models

This model has a parameter that enables partial support for Instrumentation Trace Macrocell (ITM). In hardware or RTL, trace data from ITM is sent in packets to the trace block serially using a single pin or wire. In the model, if it is enabled, the ITM trace data is output using an MTI trace source called ITM. The ITM trace source has an ITM_PACKET_TYPE field. The following table shows which packet types the model supports:

Table 3-148 ITM_PACKET_TYPE field values that the model supports

Field value Description Supported by model
ITM_SYNC Synchronization packet Not supported.
ITM_P_OVERFLOW Protocol: Overflow packet Not supported.
ITM_P_LOCAL_TIMESTAMP Protocol: Local timestamp packets Not supported.
ITM_P_GLOBAL_TIMESTAMP Protocol: Global timestamp packets Not supported.
ITM_P_EXTEN Protocol: Extension packet Not supported.
ITM_S_INSTRUMENTATION Source: Instrumentation packet Supported.
ITM_S_DWT_EVENT_COUNTER Hardware source: Event counter wrapping Not supported.
ITM_S_DWT_EXCEPTION Hardware source: Exception tracing Supported.
ITM_S_DWT_PC_SAMPLING Hardware source: PC sampling Not supported.
ITM_S_DWT_DATA_PC_TRACE Hardware source: DWT Data trace PC value Supported.
ITM_S_DWT_DATA_ADDRESS_TRACE Hardware source: DWT Data trace address value Supported.
ITM_S_DWT_DATA_DATA_TRACE Hardware source: DWT Data trace DATA value Supported.

Note:

TCMs are modeled internally and the model does not support external TCMs or the ports associated with them.

Table 3-149 Ports

Name Protocol Type Description
ahbd PVBus Slave Debug AHB - core bus slave driven by the DAP.
ahbp_m PVBus Master The core will generate Vendor System data accesses on this port.
ahbs PVBus Slave External master (e.g. DMA) can write TCMs (whether or not enabled in xTCMCR).
auxfault 2.7.4 Value protocol Slave This is wired to the Auxiliary Fault Status Register.
bigend 2.7.2 Signal protocol Slave Configure big endian data format.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
cpuwait 2.7.2 Signal protocol Slave When this signal is HIGH out of reset, it forces the processor into a quiescent state that delays its boot-up sequence and instruction execution until this signal is driven LOW
currpri 2.7.4 Value protocol Master Current execution priority.
dap_s PVBus Slave Debug Access Port (DAP).
dbgen 2.7.2 Signal protocol Slave Invasive debug enable.
dbgrestart 2.7.2 Signal protocol Slave External debug request.
dbgrestarted 2.7.2 Signal protocol Master External debug request.
edbgrq 2.7.2 Signal protocol Slave External debug request.
event 2.7.2 Signal protocol Peer This peer port of event input (and output) is for wakeup from WFE and corresponds to the RTL TXEV and RXEV signals.
fpudisable 2.7.2 Signal protocol Slave Configure core with no FPU on reset.
fpxxc 2.7.4 Value protocol Master Port which sends the value of the FPXXC cumulative exception flags.
halted 2.7.2 Signal protocol Master External debug request.
initvtor 2.7.4 Value protocol Slave Initial value of the Vector Table Offset Register (VTOR)
intisr[240] 2.7.2 Signal protocol Slave This signal array delivers signals to the NVIC.
intnmi 2.7.2 Signal protocol Slave Configure non maskable interrupt.
lockup 2.7.2 Signal protocol Master Asserted when the processor is in lockup state.
mpudisable 2.7.2 Signal protocol Slave Configure core with no MPU on reset.
niden 2.7.2 Signal protocol Slave Non-invasive debug enable.
poreset 2.7.2 Signal protocol Slave Raising this signal will do a power-on reset of the core.
pv_ppbus_m PVBus Master The core will generate External Private Peripheral Bus requests on this port.
pvbus_m PVBus Master The core will generate bus requests on this port.
sleepdeep 2.7.2 Signal protocol Master Asserted when the processor is in deep sleep.
sleeping 2.7.2 Signal protocol Master Asserted when the processor is in sleep.
stcalib 2.7.4 Value protocol Slave This is the calibration value for the SysTick timer.
stclk ClockSignal Slave This is the reference clock for the SysTick timer.
sysreset 2.7.2 Signal protocol Slave Raising this signal will put the core into reset mode (but does not reset the debug logic).
sysresetreq 2.7.2 Signal protocol Master Asserted to indicate that a reset is required.
ticks 2.6.3 InstructionCount protocol Master Port allowing the number of instructions since startup to be read from the CPU.

Table 3-150 Parameters for ARM_Cortex-M7

Name Type Default value Description
BIGENDINIT bool 0x0 Initialize processor to big endian mode
DBGLVL int 0x1 0: 2 DWT, 4 FPB; 1: 4 DWT, 8 FPB comparators
DP_FLOAT bool 0x1 Support 8-byte floats
INITVTOR int 0x0 vector-table offset at reset
LVL_WIDTH int 0x3 Number of bits of interrupt priority
NUM_IRQ int 0x20 Number of user interrupts
NUM_MPU_REGION int 0x10 Number of MPU regions
TRC bool 0x1 Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
WIC bool 0x1 Include support for WIC-mode deep sleep
cpi_div int 0x1 divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 multiplier for calculating CPI (Cycles Per Instruction)
dcache-size int 0x8000 L1 D-cache size in bytes
dcache-state_modelled bool 0x0 Set whether D-cache has stateful implementation
dcache-ways int 0x4 L1 D-cache ways (sets are implicit from size)
dtcm_enable bool 0x0 Enable DTCM at reset
dtcm_size int 0x100 DTCM size in KB
duplicate_CADI_TCM_writes bool 0x0 CADI writes to TCMs are also sent to downstream memory at same addresses (for validation platforms)
icache-size int 0x8000 L1 I-cache size in bytes
icache-state_modelled bool 0x0 Set whether I-cache has stateful implementation
icache-ways int 0x2 L1 I-cache ways (sets are implicit from size)
itcm_enable bool 0x0 Enable ITCM at reset
itcm_size int 0x100 ITCM size in KB
master_id int 0x0 Master ID presented in bus transactions
min_sync_level int 0x0 force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
scheduler_mode int 0x0 Control the interleaving of instructions in this processor (0=default long quantum, 1=low latency mode, short quantum and signal checking, 2=lock-breaking mode, long quantum with additional context switches near load-exclusive instructions, 3=ISSCompare)
semihosting-Thumb_SVC int 0xab T32 SVC number for semihosting
semihosting-cmd_line string "" Command line available to semihosting SVC calls
semihosting-cwd string "" Base directory for semihosting file access.
semihosting-enable bool 0x1 Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
semihosting-heap_base int 0x0 Virtual address of heap base
semihosting-heap_limit int 0x10700000 Virtual address of top of heap
semihosting-stack_base int 0x10700000 Virtual address of base of descending stack
semihosting-stack_limit int 0x10800000 Virtual address of stack limit
vfp-present bool 0x1 Set whether the model has VFP support
Non-ConfidentialPDF file icon PDF version100964_1142_00_en
Copyright © 2014–2018 Arm Limited or its affiliates. All rights reserved.