5.15.9 TLB trace

If enabled, this source traces TLB entries that are filled and evicted by the processor.

Output syntax:

<time> <scale> <cpu> [TLB|WALKCACHE] FILL <id> <size> <virtualregime>:<paddr> {<memtype>} {<attr>=<value>}+
<time> <scale> <cpu> [TLB|WALKCACHE] EVICT <id> <size> <virtualregime>

Timestamp (decimal value).


Unit for <time>. clk indicates that the timestamp is not related to real time, but an increasing count.


Processor, or other component, that gave the instruction.

Identifies which TLB or walk cache to trace.
Size of the region being mapped.
Virtual address and regime of the region being mapped, formatted according to the common virtual regime definition.
Physical base address of mapped region, formatted according to the common address definition.
For TLB entries, the memory type of the result. One of the following options:
Device-[G|nG][R|nR][E|nE] {(<alias>)}
Device memory, where:
Gathering or nongathering.
Reordering or nonreordering.
Early write acknowledgement or not.
Device-nGnRnE was previously known as StronglyOrdered.
Normal [NonShareable|Shareable] Inner=<cachetype> Outer=<cachetype>
Normal memory, where:
For cacheable memory, Read allocate hint. (Read allocate is assumed if not specified.)
For cacheable memory, Write allocate hint.
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