3.9.27 MMU_400_BASE

MMU-400 base component. This model is written in LISA+.

MMU_400_BASE contains the following CADI targets:

  • MMU_400_BASE

MMU_400_BASE contains the following MTI components:

Table 3-314 Ports

Name Protocol Type Description
apb3_control_ns PVBus Slave If the device has been configured with APB3 control ports then this is used to address the register file with non-secure accesses. If this is the case then the apb4_control port should not be used.
apb3_control_s PVBus Slave If the device has been configured with APB3 control ports then this is used to address the register file with secure accesses. If this is the case then the apb4_control port should not be used.
apb4_control PVBus Slave If the device has been configured with APB4 control ports then this port is used -- it carries the security world with the transaction itself. If this is the case then the apb3_control_s and apb3_control_ns should not be used.
cfg_cttw_in 2.7.2 Signal protocol Slave The SoC supports coherent page walks, this is meant to be sampled at reset. However, in practice the model has to prevent the race condition between cfg_cttw being asserted at the same 'cycle' as negedge reset. Thus we actually only sample the signal on the first transaction to the SMMU or the first transition on this signal after reset. Thus in the model, we require that cfg_cttw be held for at least this period of time.
cfg_flt_irpt_ns 2.7.2 Signal protocol Master Non-secure Configuration Access Fault Interrupt In the SMMU Architecture this is called SMMU_NSgCfgIrpt.
cfg_flt_irpt_s 2.7.2 Signal protocol Master Secure Configuration Access Fault Interrupt In the SMMU Architecture this is called SMMU_gCfgIrpt.
comb_irpt_ns 2.7.2 Signal protocol Master "Non-secure combined interrupt" (cfg_flt_irpt_ns | glbl_flt_irpt_ns | cxt_irpt_ns)?
comb_irpt_s 2.7.2 Signal protocol Master "Secure combined interrupt"
cxt_irpt_ns 2.7.2 Signal protocol Master Non-secure context bank fault NOTE that there is only one context bank fault, despite there being potentially 8 contexts. As we are HW stage 2 only then we can't have any banks configured as secure (well if we do then we generate a global fault).
glbl_flt_irpt_ns 2.7.2 Signal protocol Master Global non-secure Fault Interrupt In the SMMU Architecture this is called SMMU_NSgIrpt.
glbl_flt_irpt_s 2.7.2 Signal protocol Master Global secure Fault Interrupt In the SMMU Architecture this is called SMMU_gIrpt.
identify MMU_400_BASE_IDENTIFY Master This port is a special model port that is used to take a transaction and map it to an SSD/SSD_Index and StreamID.
priv_internals MMU_400_Internals Slave For internal use only, please do not use.
pvbus_m PVBus Master This downstream port is where the translated accesses from pvbus_s emerge. If page walks are configured to come out of this port, then they will come out with the with the same attributes as described for pvbus_ptw_m.
pvbus_ptw_m PVBus Master This downstream port is where page table walk accesses come from. This is only used if configured to use a separate page table walk port. The MMU-400 will only obey DVM messages if configured to use this port. The page walks come out of this port with the following master_id and user_flags. master_id : 0xFFFFffff The user flags : user_flags[7:0] stage 1 context_id (or 0xFF if stage2 only) user_flags[15:8] stage 2 context_id (or 0xFF if stage 1 with stage 2 bypass) user_flags[18:16] stage 1 level user_flags[21:19] stage 2 level user_flags[23:22] stage 1 descriptor encoding (0=v7s, 1=v7l, 2=v8l, 3=none) user_flags[25:24] stage 2 descriptor encoding (0=v7s, 1=v7l, 2=v8l, 3=none) user_flags[31,30] adomain of the transaction NOTE that if the walk is being done for a stage 1 page walk descriptor fetch then the stage 1 level field will indicate that level. If the walk is being done for a stage 2 descriptor fetch, then the stage 2 level field will show that level. If the context-id for a stage is not valid (0xFF) then the 'level' information is 0x7.
pvbus_s PVBus Slave This port is the upstream port of the device, addresses on the port are in the VA/IPA
reset_in 2.7.2 Signal protocol Slave The reset pin.

Table 3-315 Parameters for MMU_400_BASE

Name Type Default value Description
mmu.always_secure_ssd_indices string "" Non-programmable SSD Indexes that are always secure (e.g. 0, 6, 35-64).
mmu.cfg_cttw bool 0x1 Perform coherent page table walks
mmu.dump_unpredictablity_in_user_flags bool 0x0 Override the user flags to encode unpredictable information (validation only)
mmu.number_of_contexts int 0x8 Number of context banks
mmu.number_of_smrs int 0x10 Number of stream match registers.
mmu.percent_tlbstatus_commits int 0xa Percentage of times that a poll of TLBSTATUS will commit the TLBI commands
mmu.prefetch_only_requests int 0x0 Handle prefetch-only requests by:- 0 -- deny them 1 -- use debug table walks and TLB entries 2 -- treat them as normal transactions (dangerous)
mmu.programmable_non_secure_by_default_ssd_indices string "" Programmable SSD Indexes that are by default non-secure (e.g. 0, 6, 35-84).
mmu.programmable_secure_by_default_ssd_indices string "" Programmable SSD Indexes that are by default secure (e.g. 0, 6, 35-84).
mmu.ptw_has_separate_port bool 0x1 Page Table Walks use pvbus_ptw_m
mmu.pvbus_m_is_ace_lite bool 0x1 Is pvbus_m (the downstream port that translated transaction exit) ACE-Lite
mmu.pvbus_ptw_m_is_ace_lite bool 0x1 Is pvbus_ptw_m (the downstream port that is used for walks if ptw_has_separate_port is true) ACE-Lite
mmu.seed int 0x12345678 Seed for SMMU
mmu.stream_id_width int 0x6 StreamID bit width
mmu.tlb_depth int 0x40 TLB Depth (0 means 10000). The model will perform best with more TLB entries.
mmu.use_ssd_determination_table bool 0x1 Use SSD Determination Table
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