5.15.5 Register trace

If enabled, this source traces all writes to the processor registers.

This trace source includes writes to core registers R0 to R14, X0 to X30, CPSR, and SPSR, VFP registers such as S0 to S31, D0 to D31, FPSCR, and FPEXC, and writes to system registers including CP14, CP15, and GIC. Banked registers are traced separately using the mode as a suffix to the register name, for example r13 (current register R13) and r13_mon (banked register R13).

Output syntax:

<time> <scale> {<cpu>} R <register> <value>

<time>

Timestamp (decimal value).

<scale>

Unit for <time>, which gives consistency with device-specific Tarmac Trace formats.

<cpu>

Processor, or other component, that gave the instruction.

<register>

Register name in lowercase letters. Banked core registers can have a mode appended to them with a single underscore. Banked CP14/CP15 registers have _s or _ns appended to indicate access of either the Secure or Non-secure banked register.

<value>

Hexadecimal value that is written to the register (64 bits maximum).

If the SVE plug-in is loaded in the model, there are additional registers in the program view. The output examples below show how these registers are traced when the value changes. These data values can be very large.

8463 clk cpu0 IT (8439) 000282c0:0000152282c0_NS 053fc01f O EL1h_n : SEL      z31.B,p0,z0.B,z31.B
8463 clk cpu0 R z31 00000000_00000000_00000000_00000000

R indicates a register write. z0 to z31 are the vector registers. The written data are hexadecimal digits, which are separated by an underscore every 32 bits. The length of the written data varies with the configuration, depending on the vector length.

9756 clk cpu0 IT (9732) 01000074:000011000074_NS 2518e3e0 O EL1t_n : PTRUE    p0.B,ALL
9756 clk cpu0 R p0 ffff

R indicates a register write. p0 to p15 are the predicate registers. The written data are hexadecimal digits. If they are long enough to require one, the digits are separated by an underscore every 32 bits. The length of the written data varies with the configuration, depending on the vector length. Predicate registers contain 1 bit per byte of vector register length.

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