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Hardware memory is Weakly Ordered, but Fast Models memory is Strongly Ordered.
The CT implementation executes instructions sequentially. One instruction is retired before the next starts to execute. In a real processor, multiple memory accesses can be outstanding, and can complete in a different order from their program order. Writes can also be delayed in a write-buffer.
The programmer visible effects of these behaviors is defined in the architecture as the Weakly Ordered memory model, which the programmer must be aware of when writing lock-free cluster code.
Within Fast Models, memory accesses happen in program order, effectively as if all memory is Strongly Ordered.