1.4.7 Timing in PV models
Programmer’s View (PV) models are loosely timed.
- Caches and write buffers are not modeled,
so all memory access timing is effectively zero wait state.
- All instructions execute, in aggregate, in one cycle
of the component master clock input.
- Interrupts are not taken at every instruction boundary.
- Some sequences of instructions are executed atomically, ahead of the master clock
of a component, so that system time does not advance during execution. This difference in
behavior can affect sequential access of device registers, where devices are expecting
time to move on between accesses.
- DMA to and from Tightly Coupled Memory (TCM) is atomic.
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