1.4.8 VIC ports in PV models

The ARMCortexR4CT and ARMCortexR5xnCT models implement a simplified model of the Vectored Interrupt Controller (VIC) port.

The protocol consists of two ports:

  • The vic_addr port signals the vectored interrupt address from the external VIC.
  • The vic_ack port signals the VIC that an interrupt has been detected and is being serviced.

The expected interrupt sequence is:

  1. The software enables the VIC interface by setting the VE bit in the CP15 control register and setting up suitable interrupt routines.
  2. The VIC asserts IRQ.
  3. Some time later, the processor detects and responds to the IRQ by asserting vic_ack.
  4. The VIC writes the vector address to the processor using vic_addr.
  5. The processor de-asserts vic_ack.
  6. The processor transfers control to the vectored address returned from the VIC.

The interaction between the processor and the VIC is untimed after the processor acknowledges the interrupt, so certain interrupt sequences cannot occur in the code translation processor models.

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