7.8.3 Base - DebugAccessPort component

This section describes the DebugAccessPort component, a model of the Debug Access Port (DAP) for external debug connections.

DebugAccessPort - ports

This section describes the ports.

Table 7-18 DebugAccessPort ports

Name Protocol Type Description
ap_pvbus_m[2] PVBus Master Debug-access port to bus master channels 0 and 1.
clock ClockSignal Slave Clock input.
paddrdbg31 Signal Master Output signal that indicates which master the access came from, AP0 or AP1. Configurable.

DebugAccessPort - parameters

This section describes the parameters.

Table 7-19 Base Platform DebugAccessPort parameters

Name Type Allowed values Default value Description
ap0_rom_base_address uint64_t 0x0-0xffffffffffffffff 0x0 ROM base address for AP0.
ap1_rom_base_address uint64_t 0x0-0xffffffffffffffff 0x0 ROM base address for AP1.
ap0_has_debug_rom bool true, false false AP0 has a Debug ROM.
ap1_has_debug_rom bool true, false false AP1 has a Debug ROM.
ap0_set_paddrdbg31 bool true, false false Set paddrdbg31 signal during accesses on AP0.
ap1_set_paddrdbg31 bool true, false false Set paddrdbg31 signal during accesses on AP1.
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