CCI500 contains the following CADI targets:

• CCI500

CCI500 contains the following MTI components:

• 4.56 CCI500 - trace
• 4.105 PVBusSlave - trace

Model limitations

Address Decoder

• Only supports striping down to 4KiB.
• If the address decoder aborts the access, returns SLVERR rather than DECERR.

Interfaces

The model does not implement the Q-Channel and P-Channel interfaces.

Performance Monitoring Unit

• PMU counters recognize only a few event sources:
  • Slave interface events:

    3	ReadOnce.
    4	ReadClean, ReadShared, ReadNotSharedDirty, ReadUnique.
    5	MakeUnique, CleanUnique.
    6	CleanInvalid, CleanShared, MakeInvalid.
    7	DVM transaction received from upstream.
    9	Read data that is satisfied by a snoop request.

  • No events are implemented for the global events or for the master events.
• The PMU does not implement the event bus (EVNTBUS).

Register access

The register file only supports 32-bit accesses to its registers. Later versions of the CCI500 hardware support full write strobes to the register file. This limitation means that byte and halfword accesses work on the hardware but not on this version of the component.

Snoop filter RAMs

Snoop filter RAMs are not modeled. The Status Register fields that relate to the power state of the Snoop filter RAMs are undefined.

Additional port and parameter information

acchannelensx represents the ports ACCHANNELENS0-ACCHANNELENS6 on the RTL (Register Transfer Level) (assuming that there are seven upstream ports).

• Each upstream ACE port y (pvbus_s[y]) has a two bit ACCHANNELENSx.

  Bit 0 == 0

  disables DVM messages from being sent to this interface.

  Bit 1 == 0

  disables snoop messages from being sent to this interface.

• Each upstream ACE-Lite port z (pvbus_s[z]) has a one bit ACCHANNELENSx.

  Bit 0 == 0

  disables DVM messages from being sent to this interface.

The model supports various configurations with one LISA file. Each channel enable behaves as though it is one bit or two bit, as appropriate. If you send an invalid value, because of the type of the port, then the CCI model halts, producing a fatal error. Parameters set the initial values until you drive them, so if they are constant then you need not drive them.

In the RTL, the CCI500 samples the signals at reset. In the model, the CCI500 samples the signals at the first transaction. Thus any controller that produces these signals has to hold them constant for long enough.

The LISA file declares seven upstream ports. You can configure these ports with num_ace_ports and num_ace_lite_ports. The bottom num_ace_lite_ports are ACE-Lite+DVM. The next num_ace_ports are ACE. Any remaining ports are ignored; if transactions are made on them, then warnings are produced. For example, if num_ace_ports = 1 and num_ace_lite_ports = 1 then pvbus_s[1] is ACE, pvbus_s[0] is ACE-Lite+DVM and pvbus_s[6-2] are considered not to exist.