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Home > Fast Models components > SystemIP components > CCI500 |
Cache Coherent Interconnect. This model is written in C++.
CCI500 contains the following CADI targets:
CCI500 contains the following MTI components:
SLVERR
rather than DECERR
.3 | ReadOnce. |
4 | ReadClean, ReadShared, ReadNotSharedDirty, ReadUnique. |
5 | MakeUnique, CleanUnique. |
6 | CleanInvalid, CleanShared, MakeInvalid. |
7 | DVM transaction received from upstream. |
9 | Read data that is satisfied by a snoop request. |
EVNTBUS
).acchannelens
represents the ports x
ACCHANNELENS0
-ACCHANNELENS6
on the RTL (Register Transfer Level) (assuming that there are seven upstream ports).
y
(pvbus_s[y
]
) has a two bit ACCHANNELENSx
.z
(pvbus_s[z
]
) has a one bit ACCHANNELENSx
.The model supports various configurations with one LISA file. Each channel enable behaves as though it is one bit or two bit, as appropriate. If you send an invalid value, because of the type of the port, then the CCI model halts, producing a fatal error. Parameters set the initial values until you drive them, so if they are constant then you need not drive them.
In the RTL, the CCI500 samples the signals at reset. In the model, the CCI500 samples the signals at the first transaction. Thus any controller that produces these signals has to hold them constant for long enough.
The LISA file declares seven upstream ports. You can configure these ports with num_ace_ports
and num_ace_lite_ports
. The bottom num_ace_lite_ports
are ACE-Lite+DVM. The next num_ace_ports
are ACE. Any remaining ports are ignored; if transactions are made on them, then warnings are produced. For example, if num_ace_ports
= 1 and num_ace_lite_ports
= 1 then pvbus_s[1]
is ACE, pvbus_s[0]
is ACE-Lite+DVM and pvbus_s[6-2]
are considered not to exist.
Table 3-269 Ports
Name | Protocol | Type | Description |
---|---|---|---|
acchannelensx[7] |
2.7.4 Value protocol |
Slave | ACCHANNELENSx represents the ports ACCHANNELENS0..ACCHANNELENS7 on the RTL (assuming there are seven upstream ports). * each upstream ACE port 'y' (pvbus_s[y]) has a two bit ACCHANNELENSx * bit 0 == 0 -- DVM messages are disabled from being sent to this interface * bit 1 == 0 -- Snoop messages are disabled from being sent to this interface * each upstream ACE-Lite port 'z' (pvbus_s[z]) has a one bit ACCHANNELENSx * bit 0 == 0 -- DVM messages are disabled from being sent to this interface In the model, as we support a variety of configurations with a single LISA file then each port will behave as though it is one bit or two bit as appropriate. If you send a value that cannot be represented, given the width of the port, then the CCI model will halt and produce a fatal error. The assumed values of these are set by parameters until they are driven, so you need not drive them if they are constant. In the RTL, these signals are sampled at reset. Due to ordering issues w.r.t. reset() on different components then we cannot do that. Instead the signals are sampled at first transaction. Thus any controller that is producing these signals has to hold them constant for long enough. AC channel enables. |
address_decoder |
CCI500_AddressDecoderProtocol |
Master | An address decoder can be attached to the address_decoder port to choose which pvbus_s port a downstream transaction will go out of. If you do not connect an address decoder then all transactions will go out of port 0. |
dbgen |
2.7.2 Signal protocol |
Slave | Invasive debug enable. |
errirq |
2.7.2 Signal protocol |
Master | Indicates that an error response, DECERR or SLVERR, is received on the RRESP, BRESP, or CRRESP input signals, and it cannot be signaled precisely. |
evntcntoverflow[8] |
2.7.2 Signal protocol |
Master | Overflow flags for the PMU clock and counters. |
niden |
2.7.2 Signal protocol |
Slave | Non-invasive debug enable. |
pvbus_m[6] |
PVBus |
Master | Bus master ports. |
pvbus_register_file_s |
PVBus |
Slave | The slave port of the register file. |
pvbus_s[7] |
PVBus |
Slave | Bus slave ports. |
reset_in |
2.7.2 Signal protocol |
Slave | Reset the interconnect. |
reset_state_of_upstream_port[7] |
2.7.2 Signal protocol |
Slave | Tell the interconnect the reset state of the upstream ports, this can be used by the interconnect to check some aspects of the reset sequencing. If you are using force_on_from_start then you _must_ connect these pins. |
spiden |
2.7.2 Signal protocol |
Slave | Secure invasive debug enable. |
spniden |
2.7.2 Signal protocol |
Slave | Secure privileged non-invasive debug enable. |
Table 3-270 Parameters for CCI500
Name | Type | Default value | Description |
---|---|---|---|
acchannelens0 |
int |
0x0 |
For upstream port 0 determine if it is enabled or not w.r.t. snoop requests. |
acchannelens1 |
int |
0x0 |
For upstream port 1 determine if it is enabled or not w.r.t. snoop requests. |
acchannelens2 |
int |
0x0 |
For upstream port 2 determine if it is enabled or not w.r.t. snoop requests. |
acchannelens3 |
int |
0x0 |
For upstream port 3 determine if it is enabled or not w.r.t. snoop requests. |
acchannelens4 |
int |
0x0 |
For upstream port 4 determine if it is enabled or not w.r.t. snoop requests. |
acchannelens5 |
int |
0x0 |
For upstream port 5 determine if it is enabled or not w.r.t. snoop requests. |
acchannelens6 |
int |
0x0 |
For upstream port 6 determine if it is enabled or not w.r.t. snoop requests. |
addr_width |
int |
0x28 |
The bit-width of the address that the CCI can accept. |
cache_state_modelled |
bool |
0x1 |
Model the cache state. |
dbgen |
bool |
0x1 |
Invasive debug enable. If true, enables the counting of PMU events. |
enable_logger |
bool |
0x0 |
Enable PVBusLoggers for the downstream ports in the CCI model. |
force_on_from_start |
bool |
0x0 |
The interconnect will normally start up with snooping/DVM disabled. This parameter enables the upstream system of a port to be snooped if the upstream is not in reset and if ACCHANNELENSx allows it. No software driver for the interconnect is needed. Any port that could go into reset must have 'reset_state_of_upstream_port[]' reflect the reset state of that upstream system. Otherwise, the upstream system may receive snoop/DVM messages whilst in reset and may complain that it 'received a snoop request whilst it was in reset'. Do not use if software is directly controlling the interconnect. This option does not disavow the responsibility of the upstream system to clean any shared dirty data from its caches before going into reset. |
niden |
bool |
0x1 |
Whether non-secure events are allowed to be counted in the performance monitor |
num_ace_lite_ports |
int |
0x5 |
The bottom num_ace_lite_ports are ACE-Lite+DVM. |
num_ace_ports |
int |
0x2 |
The top num_ace_ports are ACE and support full coherency. |
number_of_phantom_entries |
int |
0x20 |
Number of phantom entries in the cache. Phantom entries are used by certain cache operations to hold temporary data. Usually this should be left at the default value which is safe for all systems containing up to 32 masters. |
qos_threshold_upper |
int |
0xc |
Reset value for the QoS threshold register. |
reentrancy_support |
string |
"env" | Must be one of: on/off/cacheglobal/env: 'on': hazard checking per cache line (normal mode), 'off': no hazard checking (use only for single master systems), 'cacheglobal': hazard checking globally for cache (not per cache line, testing feature, provokes more hazards than necessary), 'env' (or empty string): take value from FM_REENTRANCY_SUPPORT env var, if this is not set use 'on', default is 'env' |
spiden |
bool |
0x1 |
Secure invasive debug enable. If both SPIDEN and DBGEN are high, enables the counting of both Non-secure and Secure events. |
spniden |
bool |
0x1 |
Whether secure and non-secure events are allowed to be counted in the performance monitor |
version |
string |
"" | The version of the interconnect. Allowed versions are:- r0p0, r0p2, r1p0 |