1.3.7 Global exclusive monitor in Fast Models

This section describes the behavior of the global exclusive monitor, when cache-state-modelled is false and when it is true.

Whether cache-state-modelled is false or true, when the system enables the data caches, they implement the monitor for cacheable nonshared and shared memory using the cache coherency protocol. The monitor includes other clusters that are connected with a cache coherent interconnect. Most global monitor behavior, like exclusive granule size, is the same whether cache-state-modelled is false or true. In particular, the data caches follow behavior that the Arm® architecture prescribes in both cases. However, some behaviors do rely on the full modeling of cache functionality. An example is that the clearing of a monitor as a result of a cache line eviction does not happen with cache-state-modelled as false.

The RAMDevice component and PVBus to AMBAPV bridges do not contain global monitors. As a result, exclusive stores that reach a RAMDevice fail unless they go through an exclusive monitor. Some platforms might need a global monitor outside of the cache coherency domains. These platforms must include a system level monitor in the same place in the bus hierarchy as in the hardware. See the FVP_VE and FVP_Base example platforms for examples of how to use the PVBusExclusiveMonitor component.

Non-ConfidentialPDF file icon PDF version100964_1142_00_en
Copyright © 2014–2018 Arm Limited or its affiliates. All rights reserved.