3.9.15 DMC_400

ARM PrimeCell Dynamic Memory Controller(DMC400). This model is written in LISA+.

DMC_400 contains the following CADI targets:

  • DMC_400

DMC_400 contains the following MTI components:

DMC_400 - about

The configuration of this model by setting the registers does not generally affect accesses to main memory.

This component has no timing information, so changing the values of the timing registers has no effect on behavior. The memory models do not attach to the component, and error checking does not update registers because the model does not include the possibility of errors.

Table 3-287 Ports

Name Protocol Type Description
apb_interface PVBus Slave Slave bus interface for register access.
axi_if_in[4] PVBus Slave Slave bus for connecting to bus decoder.
axi_if_out[4] PVBus Master Master to connect to DRAM.
clr_ex_mon 2.7.2 Signal protocol Master Indicates when global monitors state is cleared.
user_status_ext 2.7.4 Value protocol Slave Allow user status to be set from outside.

Table 3-288 Parameters for DMC_400

Name Type Default value Description
ECC_SUPPORT bool 0x1 Does the controller support ECC?
IF_CHIP0 int -0x1 Set this parameter to 0 if memory is connected
IF_CHIP1 int -0x1 Set this parameter to 0 if memory is connected
IF_CHIP2 int -0x1 Set this parameter to 0 if memory is connected
IF_CHIP3 int -0x1 Set this parameter to 0 if memory is connected
MEMORY_WIDTH int 0x20 Valid widths are 16, 32 or 64 bits
diagnostics int 0x0 Diagnostics
revision_string string "r0p1" Revision
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