4.111 TLB - trace

This section describes the trace sources.

MMU_TLB_CONFLICT

TLB conflict. Fields:

ASID unsigned int
The Address Space Identifier of this TLB entry.
CORE_NUM unsigned int
Core number in a multi processor.
Hyp bool
Entry matches in Hyp state only
NS enum
Secure state in which TLB Entry will match
PAGESIZE unsigned int
Size of the region (log2)
PBASE unsigned int
Physical base address of the region.
REGIME_EL unsigned int
Entry matches in this translation regime
VBASE unsigned int
Virtual base address of the region.
VMID unsigned int
Virtual Machine Identifier
nG enum
Flag indicating whether ASID will be matched

MMU_TLB_EVICT

TLB evict. Fields:

ASID unsigned int
The Address Space Identifier of this TLB entry.
CORE_NUM unsigned int
Core number in a multi processor.
Hyp bool
Entry matches in Hyp state only
NS enum
Secure state in which TLB Entry will match
PAGESIZE unsigned int
Size of the region (log2)
PBASE unsigned int
Physical base address of the region.
REGIME_EL unsigned int
Entry matches in this translation regime
VBASE unsigned int
Virtual base address of the region.
VMID unsigned int
Virtual Machine Identifier
nG enum
Flag indicating whether ASID will be matched

MMU_TLB_FILL

TLB fill. Fields:

ASID unsigned int
The Address Space Identifier of this TLB entry.
CORE_NUM unsigned int
Core number in a multi processor.
Hyp bool
Entry matches in Hyp state only
INNERCACHE_RA bool
Is the inner cache allocate on read
INNERCACHE_TYPE enum
Inner Caching scheme (NC/MB/WA).
INNERCACHE_WA bool
Is the inner cache allocate on write
MEMTYPE enum
Memory type.
NS enum
Secure state in which TLB Entry will match
NSDesc enum
Secure state of transactions made using the TLB Entry
OUTERCACHE_RA bool
Is the outer cache allocate on read
OUTERCACHE_TYPE enum
Outer Caching scheme (NC/MB/WA).
OUTERCACHE_WA bool
Is the outer cache allocate on write
PAGESIZE unsigned int
Size of the region (log2)
PBASE unsigned int
Physical base address of the region.
PXN bool
Privileged Execute Never
REGIME_EL unsigned int
Entry matches in this translation regime
SH enum
Shareability
SIDE enum
Inst / Data.
VBASE unsigned int
Virtual base address of the region.
VMID unsigned int
Virtual Machine Identifier
X16HINT bool
16 Entry Contiguous Hint
XN bool
Execute Never
nG enum
Flag indicating whether ASID will be matched

MMU_TLB_FLUSH

TLB flush.

MMU_TLB_FLUSH_ADDR

TLB flush, match address. Fields:

ADDR unsigned int
Address
NS bool
Is Non-Secure
NSHYP bool
Is Non-Secure HYP

MMU_TLB_FLUSH_ADDR_RANGE

TLB flush, match address range. Fields:

ADDR_FIRST unsigned int
First address in range
ADDR_LAST unsigned int
Last address in range
NS bool
Is Non-Secure
NSHYP bool
Is Non-Secure HYP

MMU_TLB_FLUSH_ALL

TLB flush all entries.

MMU_TLB_FLUSH_ASID

TLB flush, match ASID. Fields:

ASID unsigned int
ASID of TLB flush

MMU_TLB_FLUSH_VMID

TLB flush, match VMID. Fields:

VMID unsigned int
VMID of TLB flush

MMU_TLB_HIT

TLB accesses hit. Fields:

ASID unsigned int
The Address Space Identifier of this TLB entry.
CORE_NUM unsigned int
Core number in a multi processor.
Hyp bool
Entry matches in Hyp state only
NS enum
Secure state in which TLB Entry will match
REGIME_EL unsigned int
Entry matches in this translation regime
SIDE enum
Inst / Data.
VADDR unsigned int
Virtual address of the access.
VMID unsigned int
Virtual Machine Identifier

MMU_TLB_MISS

TLB access miss. Fields:

ASID unsigned int
The Address Space Identifier of this TLB entry.
CORE_NUM unsigned int
Core number in a multi processor.
Hyp bool
Entry matches in Hyp state only
NS enum
Secure state in which TLB Entry will match
REGIME_EL unsigned int
Entry matches in this translation regime
SIDE enum
Inst / Data.
VADDR unsigned int
Virtual address of the access.
VMID unsigned int
Virtual Machine Identifier

MMU_TLB_SPILL

TLB removals caused by fill to a occupied slot.

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