4.51 ARM_SC300 - trace

This section describes the trace sources.

ASYNC_MEMORY_FAULT

Context ID Register write. Fields:

FAULT unsigned int
Fault status
PADDR unsigned int
Physical Address (or 0 if unavailable)

ATOMIC_END_ACCESS

Bus trace access for atomics. Fields:

ACCESS_FAIL bool
Memory access failed
ADDR unsigned int
The virtual address of the access.
ATTR unsigned int
Transaction Attributes: [11] Non-secure, [10] Privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer memory attributes, [3:0] inner memory attributes ([7]/[3] Allocate (Other Allocate when read), [6]/[2] Allocate (Other Allocate when write), [5]/[1] Modifiable, [4]/[0] Bufferable). All other bits are implementation defined
COMPARE_VALUE unsigned int
Compare value for CAS
LOAD_VALUE unsigned int
Loaded values
NSDESC unsigned int
The security state of the access.
OPERAND_VALUE unsigned int
Operation's operand
OPERATION enum
Operation type
PADDR unsigned int
The physical address of the access.
PRIV bool
Is this a privileged access?

ATOMIC_START_ACCESS

Bus trace access for atomics. Fields:

ADDR unsigned int
The virtual address of the access.
ATTR unsigned int
Transaction Attributes: [11] Non-secure, [10] Privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer memory attributes, [3:0] inner memory attributes ([7]/[3] Allocate (Other Allocate when read), [6]/[2] Allocate (Other Allocate when write), [5]/[1] Modifiable, [4]/[0] Bufferable). All other bits are implementation defined
COMPARE_VALUE unsigned int
Compare value for CAS
NSDESC unsigned int
The security state of the access.
OPERAND_VALUE unsigned int
Operation's operand
OPERATION enum
Operation type
PADDR unsigned int
The physical address of the access.
PRIV bool
Is this a privileged access?

ArchMsg.Warning.TarmacReconstructor

Unexpected event happened during Tarmac reconstruction. Fields:

REASON string
Reason

ArchMsg.Warning.dap_csw_bad_size

A write to CM3DAP CSW has an invalid size field. Fields:

DATA unsigned int
bits[2:0] are size

ArchMsg.Warning.recursive_branch

An instruction is performing a branch that targets the same instruction. If this was intended then a WFI might be more effective. Fields:

PC unsigned int
Address of instruction causing the branch

ArchMsg.Warning.recursive_exception

An instruction has generated an exception that targets the same instruction. Fields:

CPSR unsigned int
Processor state
PC unsigned int
Address of instruction causing the exception
TYPE enum
Type of exception

ArchMsg.Warning.secure_vector_fetch_from_nonsecure

Secure vector table is being fetched from Non-secure memory .

ArchMsg.warning_unpred_system_register_access

Fields:

IS_WRITE unsigned int
Write Not Read
OFFSET unsigned int
Register Offset

BRANCH_MISPREDICT

Simulating branch mispredict. Fields:

PC unsigned int
Origin address (or 0 if unavailable)

BRA_DIR

Direct branches, to immediate address. Fields:

CORE_NUM unsigned int
Core number in a multi processor.
INST_COUNT unsigned int
The core's instruction counter, starting at 1 for the first instruction.
ISET enum
The instructions set of the branch instruction.
IS_COND bool
Indicates if this is a conditional branch.
PC unsigned int
The address of the branch instruction.
TARGET_ISET enum
The instructions set after the branch.
TARGET_PC unsigned int
The address the instruction branches to.

BRA_INDIR

Indirect branches, perhaps to a register. Fields:

CORE_NUM unsigned int
Core number in a multi processor.
INST_COUNT unsigned int
The core's instruction counter, starting at 1 for the first instruction.
ISET enum
The instructions set of the branch instruction.
IS_COND bool
Indicates if this is a conditional branch.
PC unsigned int
The address of the branch instruction.
TARGET_ISET enum
The instructions set after the branch.
TARGET_PC unsigned int
The address the instruction branches to.

CCFAIL

Conditional instruction condition check fail. Fields:

COND enum
The condition of the conditional instruction.
CORE_NUM unsigned int
Core number in a multi processor.
PC unsigned int
The address of the conditional instruction.

CCFAIL_UNC

Unconditional instruction condition check fail. Fields:

COND enum
The condition of the conditional instruction.
CORE_NUM unsigned int
Core number in a multi processor.
PC unsigned int
The address of the conditional instruction.

CCPASS

Conditional instruction condition check pass. Fields:

COND enum
The condition of the conditional instruction.
CORE_NUM unsigned int
Core number in a multi processor.
PC unsigned int
The address of the conditional instruction.

CCPASS_UNC

Unconditional instruction condition check pass. Fields:

COND enum
The condition of the conditional instruction.
CORE_NUM unsigned int
Core number in a multi processor.
PC unsigned int
The address of the conditional instruction.

CODE_CACHE_MAINT

Code cache maintenance. Fields:

TYPE enum
Request type.
VA_END_INCL unsigned int
Inclusive end addres for by VA requests
VA_START unsigned int
Start address for by VA requests

COMPILE_BLOCK_END

Last instruction of basic block translated. Fields:

VADDR unsigned int
Address of next instruction after this basic block

COMPILE_BLOCK_START

First instruction of basic block translated. Fields:

VADDR unsigned int
Address of first instruction in basic block

COMPILE_INST

ARM instruction compiled. Fields:

DISASS string
Disassembly of the instruction.
ISET enum
The instruction set of this instruction.
ITSTATE unsigned int
The ITSTATE current for the instruction.
OPCODE unsigned int
The opcode of the instruction.
PC unsigned int
The address of the instruction.
SIZE unsigned int
The size of the instruction in bytes.

CONTEXTIDR

Context ID Register write. Fields:

CORE_NUM unsigned int
Core number in a multi processor.
NS bool
Secure or nonsecure banked register is accessed.
UNDEF bool
The register accessed is undefined.
VALUE unsigned int
The new value written.

CONTEXT_SYNC

Called for every context synchronization event. Fields:

ARCH_CSE bool
Architectural Context Synchronization Event
SYSREG_SYNC bool
System register synchronization event

CORE_ENDIAN

Core BE8 Big-Endian state changed. Fields:

BE8 bool
Core BE8 Big-Endian state

CORE_INFO

Static processor attributes. Only triggered by a call to DumpState(). Fields:

ARCH_PROFILE enum
The architecture profile of the core.
CLUSTER_ID unsigned int
The cluster ID of this processor.
CORE_NUM unsigned int
The number of this core in an MP processor.
FPU_VERSION enum
The VFP version implemented by the core.
MEM_ARCH enum
The memory architecture of the core.
NUM_CORES unsigned int
The number of cores in this MP processor.
QUANTUM_SIZE unsigned int
The default quantum size of the core.
SECURITY_FEATURES bool
Does the core have security features?

CORE_LOADS

Processor load accesses. Fields:

ACCESS_TYPE enum
The type of instruction performing the access.
ACQREL enum
Is this an acquire/release
ATTR unsigned int
Memory attributes: [11] Non-secure, [10] Privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer memory attributes, [3:0] inner memory attributes ([7]/[3] Allocate (Other Allocate when read), [6]/[2] Allocate (Other Allocate when write), [5]/[1] Modifiable, [4]/[0] Bufferable). All other bits are implementation defined
ATTR2 unsigned int
Second page memory attributes: [11] Non-secure, [10] Privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer memory attributes, [3:0] inner memory attributes ([7]/[3] Allocate (Other Allocate when read), [6]/[2] Allocate (Other Allocate when write), [5]/[1] Modifiable, [4]/[0] Bufferable). All other bits are implementation defined
CURRENT_TIME unsigned int
The core's current time, as simulated time plus local time.
DATA unsigned int
The data read or written.
ELEMENT_SIZE unsigned int
Width of each element.
LOCAL_TIME unsigned int
The core's local time, relative to the current quantum.
LOCK enum
Normal, exclusive or locked access.
NSDESC unsigned int
The physical address non-secure bit.
NSDESC2 unsigned int
The second page physical address non-secure bit.
PADDR unsigned int
The physical (translated) address.
PADDR2 unsigned int
If different from PADDR, the physical address of the second page of the access.
RESPONSE enum
0=Aborted, 1=OK, 2=Exclusive Failed
SIZE unsigned int
Width of the access in bytes. Only required if DATA is not traced.
TRANS bool
Is this a translated access.
VADDR unsigned int
The virtual address of the access.

CORE_REGS

Changes of the core registers R0 to R14. Fields:

CORE_NUM unsigned int
Core number in a multi processor.
ID unsigned int
The register number, 0 to 14.
OLD_VALUE unsigned int
The old value overwritten.
PHYS_ID enum
The physical register accessed.
VALUE unsigned int
The new value written to the register.

CORE_STORES

Processor store accesses. Fields:

ACCESS_TYPE enum
The type of instruction performing the access.
ACQREL enum
Is this an acquire/release
ATTR unsigned int
Memory attributes: [11] Non-secure, [10] Privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer memory attributes, [3:0] inner memory attributes ([7]/[3] Allocate (Other Allocate when read), [6]/[2] Allocate (Other Allocate when write), [5]/[1] Modifiable, [4]/[0] Bufferable). All other bits are implementation defined
ATTR2 unsigned int
Second page memory attributes: [11] Non-secure, [10] Privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer memory attributes, [3:0] inner memory attributes ([7]/[3] Allocate (Other Allocate when read), [6]/[2] Allocate (Other Allocate when write), [5]/[1] Modifiable, [4]/[0] Bufferable). All other bits are implementation defined
CURRENT_TIME unsigned int
The core's current time, as simulated time plus local time.
DATA unsigned int
The data read or written.
ELEMENT_SIZE unsigned int
Width of each element.
LOCAL_TIME unsigned int
The core's local time, relative to the current quantum.
LOCK enum
Normal, exclusive or locked access.
NSDESC unsigned int
The physical address non-secure bit.
NSDESC2 unsigned int
The second page physical address non-secure bit.
PADDR unsigned int
The physical (translated) address.
PADDR2 unsigned int
If different from PADDR, the physical address of the second page of the access.
RESPONSE enum
0=Aborted, 1=OK, 2=Exclusive Failed
SIZE unsigned int
Width of the access in bytes. Only required if DATA is not traced.
TRANS bool
Is this a translated access.
VADDR unsigned int
The virtual address of the access.

CRYPTO_SPEC

Every crypto instruction speculatively executed.

DATA_CACHE_ZERO

Zero and invalidate cache line from DC ZVA instruction. Fields:

RESPONSE enum
0=Aborted, 1=OK
SIZE unsigned int
The size of zero'd memory in bytes.
VADDR unsigned int
Virtual address of the zero'd cache line.

DEBUG_EVENT

Hardware debug support event. Fields:

EVENT enum
Description of event
VALUE unsigned int
data value

DWT_MATCH

DWT comparator matches. Fields:

NUM unsigned int
DWT comparator number
TYPE enum
DWT comparator configuration

END_COMPILE

Compilation end. Fields:

END_OF_PAGE_COUNT unsigned int
Number of basic blocks exited due to page boundary since START_COMPILE.
FETCHFAIL_COUNT unsigned int
Number of basic blocks exited due to ifetch failure START_COMPILE.
INST_COUNT unsigned int
Number of instructions compiled since START_COMPILE.
NONSEQ_COUNT unsigned int
Number of basic blocks exited due to non-sequential instructions since START_COMPILE.
PAGE_STRADDLE_COUNT unsigned int
Number of basic blocks exited due to unaligned instructions crossing page since START_COMPILE.

EXCEPTION

Exceptions which are taken. Fields:

CORE_NUM unsigned int
Core number in a multi processor.
ISET enum
The instruction set of the processor when the exception occurred.
LR unsigned int
The value assigned to the link register.
PC unsigned int
The location where the exception occurred.
TARGET_ISET enum
The instruction set of the exception handler code.
TARGET_PC unsigned int
The address the exception branches to.
VECTOR enum
The exception vector.

EXCEPTION_END

Every exception completed.

EXCEPTION_ENTRY

Event marking the entry of an exception. All pushes of register to the stack will follow this event. Fields:

PC unsigned int
The location where the exception occurred.
VECTOR enum
The exception that occurred.

EXCEPTION_RAISE

Every exception raised.

EXCEPTION_RETURN

Marks the end of an exception, but on an M core does not indicate a program flow change (branch). In most situations it will be followed by an indirect branch. Fields:

CORE_NUM unsigned int
Core number in a multi processor.
INST_COUNT unsigned int
The core's instruction counter, starting at 1 for the first instruction.
ISET enum
The instructions set of the branch instruction.
PC unsigned int
The address of the branch instruction.

EXCEPTION_RETURN_PREBRANCH

Exception return event that must occur before PC and processor state have updated.

EXCEPTION_START

Every exception started.

EXCEPTION_VECTOR_FETCH

I-side vector fetch for M-class exception. Fields:

CORE_NUM unsigned int
Core number in a multi processor.
DATA unsigned int
Result of fetch if OK
RESPONSE enum
0=Aborted, 1=OK
VADDR unsigned int
Where the vector is fetched from (including VTOR)

HLT

HLT instruction occurred. Fields:

IMM16 unsigned int
The 16-bit immediate value encoded in HLT instruction.

INFO_EXCEPTION_REASON

Provide information of real cause of exception. Fields:

FaultCause enum
Which bit of which V7M/V8M-mainline FSR/HFSR would have been set.
PC unsigned int
The location where the exception occurred.
PHASE enum
What we are doing with the exception.
REASONS enum
Why we are doing it.
VECTOR enum
The exception that occurred.

INFO_STACKING

Provide information of real cause of exception. Fields:

PHASE enum
Are we starting or ending a sequence of stack writes.
REASONS enum
Why we are doing it.

INST

Every instruction executed. Fields:

CORE_NUM unsigned int
Core number in a multi processor.
CURRENT_TIME unsigned int
The core's current time, as simulated time plus local time.
DISASS string
Disassembly of instruction.
INST_COUNT unsigned int
The core's instruction counter, starting at 1 for the first instruction.
ISET enum
The current instruction set.
ITSTATE unsigned int
The current ITSTATE.
LOCAL_TIME unsigned int
The core's local time, relative to the current quantum.
MODE enum
The mode the core is in.
NSDESC unsigned int
The physical address non-secure bit.
NSDESC2 unsigned int
The second page physical address non-secure bit.
OPCODE unsigned int
The opcode of the instruction.
PADDR unsigned int
The physical address of the instruction.
PADDR2 unsigned int
If different from PADDR, the physical address of the second page of the instruction.
PC unsigned int
The address of the instruction.
SIZE unsigned int
The size of the instruction in bytes.

INST_END

Every instruction completed.

INST_START

Every instruction started. Fields:

ISET enum
The current instruction set.
MODE enum
The mode the core is in.
NS enum
The current Secure State.
PC unsigned int
The address of the conditional instruction.

INST_STRADDLE

Instruction straddles boundary.

ITM

Instrumentation Trace Macrocell. Fields:

ITM_PACKET_TYPE enum
ITM and DWT packets type.
PACKET_HEADER unsigned int
ITM Packet Header.
PACKET_PAYLOAD unsigned int
ITM Packet Payload.

LOCAL_MONITOR

Local monitor activity. Fields:

PADDR unsigned int
Local Monitor Address
State enum
State of the monitor (Open/Exclusive)

LOCKUP_CYCLE

This event is triggered if the core enters or stays in the lock-up state. Fields:

CAUSE enum
What causes the lockup?.

LOCKUP_ENTRY

This event is triggered if the core enters the lock-up state. Fields:

PC unsigned int
The PC when the lockup state is entered.

LOCKUP_EXIT

This event is triggered if the core leaves the lock-up state.

MODE_CHANGE

Mode change. Fields:

CORE_NUM unsigned int
Core number in a multi processor.
MODE enum
The new mode.
OLD_MODE enum
The old mode.

MPU_TRANS

Address translation information. Fields:

CORE_NUM unsigned int
Core number in a multi processor.
EXEC_PERM enum
Execution Permission
INNERCACHE_RA bool
Is the inner cache allocate on read
INNERCACHE_TYPE enum
Inner Caching scheme (NC/MB/WA).
INNERCACHE_WA bool
Is the inner cache allocate on write
MEMTYPE enum
Memory type.
OUTERCACHE_RA bool
Is the outer cache allocate on read
OUTERCACHE_TYPE enum
Outer Caching scheme (NC/MB/WA).
OUTERCACHE_WA bool
Is the outer cache allocate on write
PADDR unsigned int
Address of the access.
PAGESIZE unsigned int
Page size as log2(size).
READ_PERM enum
Read Permission
REG_NUM signed int
MPU region-number 0-15 (else 0xFF=none, 0xBB/0xDD=background/default)
SH enum
Shareability
SIDE enum
Inst / Data.
WRITE_PERM enum
Write Permission

PERIODIC

Called for every quantum. Fields:

CORE_NUM unsigned int
Core number in a multi processor.
INST_COUNT unsigned int
The instruction count of this CPU.
PC unsigned int
The address of the next instruction to be executed on this CPU.

PPB_READ_ACCESS

Trace reads from the core to memory mapped registers in the PPB (private peripheral bus) address range. Fields:

ACCESS_SIZE unsigned int
Logarithm of the access size: 0=byte, 1=halfword, 2=word, 3=doubleword, ...
BURST_LEN unsigned int
The number of data transfers (beats) in this burst.
DATA unsigned int
The data transferred.
INNER_ATTRIBUTES unsigned int
The inner attributes: bit0=write allocate, bit1=read allocate, bit2=cachable, bit3=bufferable, bit4=shareable.
INST bool
Is an instruction fetch.
LOCK enum
Normal / Locked / Exclusive.
MASTER_ID unsigned int
The AXI master ID.
NS bool
Is a nonsecure access.
OUTER_ATTRIBUTES unsigned int
The outer attributes: bit0=write allocate, bit1=read allocate, bit2=cachable, bit3=bufferable, bit4=shareable.
PADDR unsigned int
Physical address of access.
PRIV bool
Is privileged access.
RESPONSE enum
Whether the transaction was successful, or an error occurred.
USER_FLAGS unsigned int
Core specific additional signals.

PPB_WRITE_ACCESS

Trace writes from the core to memory mapped registers in the PPB (private peripheral bus) address range. Fields:

ACCESS_SIZE unsigned int
Logarithm of the access size: 0=byte, 1=halfword, 2=word, 3=doubleword, ...
BURST_LEN unsigned int
The number of data transfers (beats) in this burst.
DATA unsigned int
The data transferred.
INNER_ATTRIBUTES unsigned int
The inner attributes: bit0=write allocate, bit1=read allocate, bit2=cachable, bit3=bufferable, bit4=shareable.
INST bool
Is an instruction fetch.
LOCK enum
Normal / Locked / Exclusive.
MASTER_ID unsigned int
The AXI master ID.
NS bool
Is a nonsecure access.
OUTER_ATTRIBUTES unsigned int
The outer attributes: bit0=write allocate, bit1=read allocate, bit2=cachable, bit3=bufferable, bit4=shareable.
PADDR unsigned int
Physical address of access.
PRIV bool
Is privileged access.
RESPONSE enum
Whether the transaction was successful, or an error occurred.
USER_FLAGS unsigned int
Core specific additional signals.

PRELOAD_DATA

Data preload from PLD instruction. Fields:

VADDR unsigned int
Virtual address of the data that should be preloaded.

PRELOAD_INST

Instruction preload from PLI instruction. Fields:

VADDR unsigned int
Virtual address of the instruction that should be preloaded.

PRE_CORE_LOAD

Trace just before a core load. Fields:

CURRENT_TIME unsigned int
The core's current time, as simulated time plus local time.
LOCAL_TIME unsigned int
The core's local time, relative to the current quantum.

PRE_CORE_STORE

Trace just before a core store. Fields:

CURRENT_TIME unsigned int
The core's current time, as simulated time plus local time.
LOCAL_TIME unsigned int
The core's local time, relative to the current quantum.

RUN_STATE

Run state transition. Fields:

INST_COUNT unsigned int
Ticks count at point of transition.
NEW enum
New run state.
OLD enum
Old run state.

SEMIHOSTING_CALL

Call of a semihost function occurred. Fields:

PC unsigned int
The program counter after the semihosting call.

SEMIHOSTING_PRECALL

About to call semihost. Fields:

NS bool
Is Non-Secure.
REG_WIDTH unsigned int
The current register width in bytes.

SIGNAL

External signal state change. Fields:

SIGNAL enum
Signal that changed
STATE bool
Signal asserted state

START_COMPILE

Compilation started. Fields:

VADDR unsigned int
Instruction where compilation begins.

SYNC

Called for every synchronization. Fields:

CORE_NUM unsigned int
Core number in a multi processor.
INST_COUNT unsigned int
The instruction count of this CPU.
LOCAL_QUANTUM unsigned int
The local quantum of this CPU.
LOCAL_TIME unsigned int
The local time of this CPU.

SYSCALL

System call instruction executed. Fields:

IMM unsigned int
Immediate value of the system call instruction.
TYPE enum
System call type.
VADDR unsigned int
Instruction that caused the system call.

SYSREG_READ

Trace reads from system registers. Fields:

REG_NAME enum
Register number
VALUE unsigned int
The value read.

SYSREG_UPDATE32

Triggers when the system updates a register. Fields:

REG enum
Register number.
UNKNOWN unsigned int
Bits of the register which became unknown.
VALUE unsigned int
Value written to the register.

SYSREG_UPDATE64

Triggers when the system updates a register. Fields:

REG enum
Register number.
UNKNOWN unsigned int
Bits of the register which became unknown.
VALUE unsigned int
Value written to the register.

SYSREG_WRITE

Trace write to system registers. Fields:

REG_ACCESS enum
Register access status
REG_NAME enum
Register number
UPDATED_VALUE unsigned int
Updated value of the register now it has been written.
VALUE unsigned int
Value written to the register.

UNALIGNED_LDST_RETIRED

Processor unaligned load/store. Fields:

ACCESS_SIZE unsigned int
Log2 of the access width in bytes used for alignment checking (1=>half-word, 2->word ...)
NUMBER_OF_BEATS unsigned int
Number of accesses (beats) in this burst (Total size in bytes is ACCESS_SIZE * NUMBER_OF_BEATS)
VADDR unsigned int
The virtual address of the access

WAYPOINT

Signals end of basic block execution. Fields:

CORE_NUM unsigned int
Core number in a multi processor.
ISET enum
Origin instructions set
IS_COND bool
Indicates if this is a conditional waypoint.
PC unsigned int
Origin address (or 0 if unavailable)
TAKEN bool
Indicates if this waypoint was taken.
TARGET unsigned int
Destination address
TARGET_ISET enum
Destination instructions set

WFE_END

WFE ended. Fields:

INST_COUNT unsigned int
Ticks count when leaving WFE.

WFE_EVENT_REGISTER

WFE event register status: set/clear, reason. Fields:

INST_COUNT unsigned int
Ticks count.
REASON enum
Reason for set/clear. Only REASON==0 (Cleared by WFE) clears the bit, all other reasons set it.

WFE_IGNORED

WFE ignored. Fields:

EVENT bool
This WFE was ignored because the event register was set.
INST_COUNT unsigned int
Ticks count when ignoring WFE.
TRAPPED bool
This WFE was trapped.

WFE_START

WFE entered. Fields:

INST_COUNT unsigned int
Ticks count when entering WFE.

WFI_END

WFI ended. Fields:

INST_COUNT unsigned int
Ticks count when leaving WFI.

WFI_IGNORED

WFI ignored. Fields:

DISABLED bool
This WFI was ignored because WFI is disabled.
INST_COUNT unsigned int
Ticks count when ignoring WFI.
REASON enum
specifies reason why WFI trace was ignored
TRAPPED bool
This WFI was trapped.

WFI_START

WFI entered. Fields:

INST_COUNT unsigned int
Ticks count when entering WFI.

WFI_WAKEUP

WFI wakeup. Fields:

INST_COUNT unsigned int
Ticks count when WFI wakeup occurred.
REASON enum
Reason for wakeup.

XPSR

Changes to the xPSR register. Fields:

CORE_NUM unsigned int
Core number in a multi processor.
OLD_VALUE unsigned int
The old xPSR value
UNKNOWN unsigned int
Bits within the register that have unknown value.
VALUE unsigned int
The new xPSR value
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