3.9.40 PL080_DMAC

ARM PrimeCell DMA Controller(PL080/081). This model is written in LISA+.

PL080_DMAC contains the following CADI targets:

  • ClockTimerThread
  • ClockTimerThread64
  • PL080_DMAC
  • SchedulerThread
  • SchedulerThreadEvent

PL080_DMAC contains the following MTI components:

PL080_DMAC - about

This component provides 8 configurable DMA channels, and 16 DMA ports for handshaking with peripherals. You can configure each channel to operate in one of eight flow control modes either under DMA control or the control of the source or destination peripheral. Transfers can occur on either master channel and can optionally be endian converted on both source and destination transfers.

Performance

This component might have a significant impact on system performance in certain flow control modes.

Channels configured for small bursts, or using single bursts, and with peripheral DMA handshaking could add significant overheads. The peripheral has not been fully optimized to make use of the advanced features of the PVBus model.

Table 3-336 Ports

Name Protocol Type Description
clk_in ClockSignal Slave Clock signal to control DMA transfer rate.
dma_port[16] 2.4.11 PL080_DMAC_DmaPortProtocol protocol Slave request/response ports for communicating with devices.
interr 2.7.2 Signal protocol Master DMA error interrupt signal.
intr 2.7.2 Signal protocol Master Combined DMA error and terminal count signal.
inttc 2.7.2 Signal protocol Master DMA terminal count signal.
pvbus0_m PVBus Master Master bus interface 0 for DMA transfers.
pvbus1_m PVBus Master Master bus interface 1 for DMA transfers.
pvbus_s PVBus Slave Slave port for register accesses.
reset_in 2.7.2 Signal protocol Slave System reset.

Table 3-337 Parameters for PL080_DMAC

Name Type Default value Description
activate_delay int 0x0 request delay
fifo_size int 0x10 Channel FIFO size in bytes
generate_clear bool 0x0 Generate clear response
max_transfer int 0x100 Largest atomic transfer
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