3.9.42 PL111_CLCD

ARM PrimeCell Color LCD Controller(PL111). This model is written in LISA+.

PL111_CLCD contains the following CADI targets:

  • ClockTimerThread
  • ClockTimerThread64
  • PL111_CLCD
  • PL11x_CLCD
  • SchedulerThread
  • SchedulerThreadEvent

PL111_CLCD contains the following MTI components:

PL111_CLCD - about

This component implements the hardware cursor of the PL111_CLCD, which is the main change compared with PL110.

Table 3-341 Ports

Name Protocol Type Description
clk_in ClockSignal Slave Master clock input, typically 24MHz, to drive pixel clock timing.
control 2.7.4 Value protocol Slave Auxiliary control register 1.
display 2.4.7 LCD protocol Master Connection to visualization component.
intr 2.7.2 Signal protocol Master Interrupt signaling for flyback events.
pvbus PVBus Slave Slave port for register access.
pvbus_m PVBus Master DMA port for video data.

Table 3-342 Parameters for PL111_CLCD

Name Type Default value Description
disable_snooping_dma bool 0x0 Disable DMA snooping
pixel_double_limit int 0x12c Minimum LCD pixel width before display will be zoomed

Table 3-343 Parameters for PL11x_CLCD

Name Type Default value Description
pl11x_clcd.disable_snooping_dma bool 0x0 Disable DMA snooping
pl11x_clcd.pixel_double_limit int 0x12c Minimum LCD pixel width before display will be zoomed
pl11x_clcd.pl11x_behavior int 0x0 Define PL11x behaviour. 0 for PL110, 1 for PL111
Non-ConfidentialPDF file icon PDF version100964_1142_00_en
Copyright © 2014–2018 Arm Limited or its affiliates. All rights reserved.