3.2.11 PVBusSlave

A PVBusSlave handles incoming transactions, and handles support for mapping regions of device address space to work as RAM/ROM/device memory. This model is written in C++.

PVBusSlave contains the following MTI components:

PVBusSlave - about

Any component that acts as a bus slave must:

  • Provide a PVBus slave port.
  • Instantiate a PVBusSlave subcomponent, with the size parameter configured for the address range covered by the device.
  • Connect the slave port to the pvbus_s port on the PVBusSlave.

By default, the PVBusSlave translates all transactions into read() and write() requests on the device port.

The control port enables you to configure the PVBusSlave for a device. This lets you define the behavior of the different regions of the address space on the device. You can configure regions separately for read and write, at a 4KB granularity. This permits you to set memory-like, device-like, abort, or ignore access address regions.

Transactions to memory-like regions are handled internally by the PVBusSlave subcomponent. Abort and ignore regions are also handled by the PVBusSlave.

Transactions to device-like regions are forwarded to the device port. Your device must implement the read() and write() methods on the device port if any regions are configured as device-like.

Performance

This component typically does not significantly affect the performance of a PV system. However, correct implementation of the PVBusSlave component is critical to the performance of the overall PV system. For example, routing a request to a PVDevice port is slower than letting the PVBusSlave component handle the request internally. ARM recommends using the internal support for memory-like regions where possible.

pv::accessMode values

The values assigned to pv::accessMode control what happens when an address is accessed. Legal values for the enumeration are:

pv::ACCESSMODE_MEMORY
Act as memory. The PVBusSlave manages the underlying storage to provide 4KB of memory, which can be ROM or RAM, depending on how you configure it to handle bus write transactions.
pv::ACCESSMODE_DEVICE
Act as a device. Requests to the select pages are routed to the PVBusSlave device port, where the necessary behavior can be implemented by the component.
pv::ACCESSMODE_ABORT
Generate bus abort signals for any accesses to this page.
pv::ACCESSMODE_IGNORE
Ignore accesses to this page. Bus read requests return 0.

Table 3-56 Ports

Name Protocol Type Description
control 2.4.13 PVBusSlaveControl protocol Slave Enables the owning component to control which regions of the device memory are to be handled as RAM/ROM/Device. These settings can be changed dynamically. For example, when a Flash component is being programmed, it can switch to treating reads as Device requests instead of ROM requests.
device 2.4.14 PVDevice protocol Master Passes on requests for peripheral register accesses to permit the owning component to handle the request.
pvbus_s PVBus Slave Handles incoming requests from bus masters.
reset 2.7.2 Signal protocol Slave On the assert of this signal, a reset of the bus slave will be latched this is used by the bus deadlock detection logic.
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