Fast Models Reference Manual : 3.4.36 ARMCortexR7x1CT

ARMCortexR7x1CT contains the following CADI targets:

ARM_Cortex-R7
Cluster_ARM_Cortex-R7
PVCache

ARMCortexR7x1CT contains the following MTI components:

Note:

An ARMCortexR7x2CT component also exists.
The per-core parameters are preceded by cpun., where n identifies the core (0 or 1).

Differences between the CT model and RTL implementations

This component has the following differences from the corresponding revision of the RTL implementation:

This component does not implement address filtering within the SCU. The enable bit for this feature is ignored.
The GIC does not respect the CFGSDISABLE signal. This leads to some registers being accessible when they must not be.
The SCU enable bit is ignored. The SCU is always enabled.
The SCU ignores the invalidate all register.
The Broadcast TLB or cache operations in this model do not cause other cores in the cluster that are asleep because of WFI to wake up.
The RR bit in the SCTLR is ignored.
The Power Control Register in the system control coprocessor is implemented but writing to it does not change the behavior of the model.
The model cannot be configured with a 128-entry TLB.
When modeling the SCU, coherency operations are represented by a memory write followed by a read to refill from memory, rather than using cache-to-cache transfers.
TCMs are modeled internally and the model does not support external TCMs or the ports associated with them.

Caches

This component implements L1 cache as architecturally defined, but does not implement L2 cache. If you require an L2 cache you can add a PL310 Level 2 Cache Controller component.

Debug features

All core, VFP, and CP15 registers are visible in the debugger. The CP14 DSCR register is visible for compatibility with some debuggers. This register has no defined behavior. This component also exports the SCU, Watchdog/Timer and GIC registers.

This component directly supports single-address unconditional instruction breakpoints, unconditional instruction address range breakpoints, and single-address unconditional data breakpoints. The debugger might augment these with more complex combinations of breakpoints.

The model does not support CADI exception breakpoints. Instead, it implements exception breakpoints as register breakpoints on pseudoregisters, named after the exceptions, in the Vectors register group.

This component presents two 4GB views of physical memory, one as seen from secure mode and one as seen from normal mode.

Additional port and parameter information

pvbus_s

Slave port to access the TCM RAM of CPU n. Bits [3:0] of the user flags in the transaction are used to select the TCM:

0 selects the ITCM of CPU 0.
1 selects the DTCM of CPU 0.
2 selects the ITCM of CPU 1.
3 selects the DTCM of CPU 1.
Any other value is reserved.

semihosting-cmd_line

The value of argv[0] points to the first command-line argument, not to the name of an image.

vfp-enable_at_reset

This is a model-specific behavior with no hardware equivalent.

Table 3-173 Ports

Name	Protocol	Type	Description
`acp_s`	`PVBus`	Slave	AXI ACP slave port.
`cfgend[1]`	`2.7.2 Signal protocol`	Slave	This signal if for EE bit initialisation.
`cfgnmfi[1]`	`2.7.2 Signal protocol`	Slave	This signal disables FIQ mask in CPSR.
`clk_in`	`ClockSignal`	Slave	The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
`clusterid`	`2.7.4 Value protocol`	Slave	The port reads the value in CPU ID register field, bits[11:8] of the MPIDR.
`event`	`2.7.2 Signal protocol`	Peer	This peer port of event input (and output) is for wakeup from WFE.
`fiq[1]`	`2.7.2 Signal protocol`	Slave	Legacy FIQ request input line.
`fiqout[1]`	`2.7.2 Signal protocol`	Master	Output of individual processor nFIQ from the interrupt controller.
`fpuflags[1]`	`2.7.6 ValueState protocol`	Master	Floating-Point Unit output flags.
`halt[1]`	`2.7.2 Signal protocol`	Slave	Raising this signal will put the core into halt mode. Equivalent to the hardware nCPUHALT[N:0] signal.
`initram[1]`	`2.7.2 Signal protocol`	Slave	This signal enables the processor to boot from the instruction TCM.
`ints[480]`	`2.7.2 Signal protocol`	Slave	Interrupt distributor interrupt lines.
`irq[1]`	`2.7.2 Signal protocol`	Slave	Legacy IRQ request input line.
`irqout[1]`	`2.7.2 Signal protocol`	Master	Output of individual processor nIRQ from the interrupt controller.
`mfilteren`	`2.7.2 Signal protocol`	Slave	This signal enables filtering of address ranges between master bus ports.
`mfilterend`	`2.7.4 Value protocol`	Slave	This port sets end of region mapped to pvbus_m1.
`mfilterstart`	`2.7.4 Value protocol`	Slave	This port sets start of region mapped to pvbus_m1.
`periphbase`	`2.7.4 Value protocol`	Slave	This port sets the base address of private peripheral region.
`periphclk_in`	`ClockSignal`	Slave	The timer and the watchdog take need a clk that is scaled down atleast by factor of two.
`periphreset`	`2.7.2 Signal protocol`	Slave	This signal resets timer and interrupt controller.
`pfilterend`	`2.7.4 Value protocol`	Slave	This port sets end of region mapped to pvbus_mp.
`pfilterstart`	`2.7.4 Value protocol`	Slave	This port sets start of region mapped to pvbus_mp.
`pmuirq[2]`	`2.7.2 Signal protocol`	Master	Interrupt signal from performance monitoring unit.
`pvbus_m0`	`PVBus`	Master	The core will generate bus requests on this port.
`pvbus_m1`	`PVBus`	Master	The core will generate bus requests on this port.
`pvbus_mp`	`PVBus`	Master	The core will generate bus requests on this port.
`pvbus_s`	`PVBus`	Slave	tcm slave port
`reset[1]`	`2.7.2 Signal protocol`	Slave	Raising this signal will put the core into reset mode.
`scureset`	`2.7.2 Signal protocol`	Slave	This signal resets SCU.
`smpnamp[1]`	`2.7.2 Signal protocol`	Master	This signals AMP or SMP mode for each Cortex-R7 processor.
`standbywfe[1]`	`2.7.2 Signal protocol`	Master	This signal indicates if a core is in WFE state.
`standbywfi[1]`	`2.7.2 Signal protocol`	Master	This signal indicates if a core is in WFI state.
`teinit[1]`	`2.7.2 Signal protocol`	Slave	This signal provides default exception handling state.
`ticks[1]`	`2.6.3 InstructionCount protocol`	Master	This port should be connected to one of the two ticks ports on a 'visualisation' component, in order to display a running instruction count.
`vinithi[1]`	`2.7.2 Signal protocol`	Slave	This signal controls of the location of the exception vectors at reset.
`wdreset[1]`	`2.7.2 Signal protocol`	Slave	This signal resets individual watchdog.
`wdresetreq[1]`	`2.7.2 Signal protocol`	Master	CPU watchdog reset requests.

Table 3-174 Parameters for Cluster_ARM_Cortex-R7

Name	Type	Default value	Description
`CLUSTER_ID`	`int`	`0x0`	Processor cluster ID value
`LOCK_STEP`	`int`	`0x0`	Affects dual-processor configurations only, and ignored by single-processor configurations. 0 - Disable. Set for two independent processors. 1 - Lock Step. Appears to the system as two processors but is internally modeled as a single processor. 3 - Split Lock. Appears to the system as two processors but can be statically configured from reset either as two independent processors or two locked processors. For the model, these are equivalent to Disable and Lock Step, respectively, except for the value of build options registers. The model does not support dynamically splitting and locking the processor.
`MFILTEREN`	`bool`	`0x0`	Enables filtering of address ranges
`MFILTEREND`	`int`	`0x0`	Specifies the end address for address filtering
`MFILTERSTART`	`int`	`0x0`	Specifies the start address for address filtering
`NUM_MPU_REGION`	`int`	`0xc`	Sets the number of MPU regions
`PERIPHBASE`	`int`	`0xae000000`	Base address of peripheral memory space
`PFILTEREND`	`int`	`0x0`	Specifies the end address for peripheral port address filtering
`PFILTERSTART`	`int`	`0xfff00000`	Specifies the start address for peripheral port address filtering
`cpi_div`	`int`	`0x1`	Divider for calculating CPI (Cycles Per Instruction)
`cpi_mul`	`int`	`0x1`	Multiplier for calculating CPI (Cycles Per Instruction)
`dcache-state_modelled`	`bool`	`0x0`	Set whether D-cache has stateful implementation
`dic-spi_count`	`int`	`0x40`	Number of shared peripheral interrupts implemented
`ecc_on`	`bool`	`0x0`	Enable Error Correcting Code
`icache-state_modelled`	`bool`	`0x0`	Set whether I-cache has stateful implementation

Table 3-175 Parameters for ARM_Cortex-R7

Name	Type	Default value	Description
`cpu0.CFGEND`	`bool`	`0x0`	Initialize to BE8 endianness
`cpu0.CFGNMFI`	`bool`	`0x0`	Enable nonmaskable FIQ interrupts on startup
`cpu0.DP_FLOAT`	`bool`	`0x1`	Sets whether double-precision instructions are available
`cpu0.INITRAM`	`bool`	`0x0`	Enable the processor to boot from the instruction TCM
`cpu0.POWERCTLI`	`int`	`0x0`	Default power control state for processor
`cpu0.SMPnAMP`	`bool`	`0x0`	Set whether the processor is part of a coherent domain
`cpu0.TEINIT`	`bool`	`0x0`	T32 exception enable. The default has exceptions including reset handled in A32 state
`cpu0.VINITHI`	`bool`	`0x0`	Initialize with high vectors enabled
`cpu0.dcache-size`	`int`	`0x8000`	Set D-cache size in bytes
`cpu0.dtcm_size`	`int`	`0x8`	DTCM size in KB
`cpu0.icache-size`	`int`	`0x8000`	Set I-cache size in bytes
`cpu0.itcm_size`	`int`	`0x8`	ITCM size in KB
`cpu0.min_sync_level`	`int`	`0x0`	Force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
`cpu0.semihosting-ARM_HLT`	`int`	`0xf000`	ARM HLT number for semihosting
`cpu0.semihosting-ARM_SVC`	`int`	`0x123456`	ARM SVC number for semihosting
`cpu0.semihosting-Thumb_HLT`	`int`	`0x3c`	Thumb HLT number for semihosting
`cpu0.semihosting-Thumb_SVC`	`int`	`0xab`	Thumb SVC number for semihosting
`cpu0.semihosting-cmd_line`	`string`	""	Command line available to semihosting SVC calls
`cpu0.semihosting-cwd`	`string`	""	Base directory for semihosting file access.
`cpu0.semihosting-enable`	`bool`	`0x1`	Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false
`cpu0.semihosting-heap_base`	`int`	`0x0`	Virtual address of heap base
`cpu0.semihosting-heap_limit`	`int`	`0xf000000`	Virtual address of top of heap
`cpu0.semihosting-hlt-enable`	`bool`	`0x0`	Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true
`cpu0.semihosting-stack_base`	`int`	`0x10000000`	Virtual address of base of descending stack
`cpu0.semihosting-stack_limit`	`int`	`0xf000000`	Virtual address of stack limit
`cpu0.tcm-present`	`bool`	`0x1`	Disables the DTCM and ITCM
`cpu0.vfp-enable_at_reset`	`bool`	`0x0`	Enable coprocessor access and VFP at reset
`cpu0.vfp-present`	`bool`	`0x1`	Set whether model has VFP support

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