3.10.57 SMSC_91C111

10/100 Non-PCI Ethernet Controller(SMSC 91C111). This model is written in C++.

SMSC_91C111 contains the following CADI targets:

  • SMSC_91C111

SMSC_91C111 contains the following MTI components:

SMSC_91C111 - about

This component provides the register interface of the SMSC part and can be configured to act as an unconnected Ethernet port, or an Ethernet port connected to the host by an Ethernet bridge.

It uses a banked register model of primarily 16-bit registers. There are also indirectly accessible registers for the PHY unit.

Table 3-404 Ports

Name Protocol Type Description
clock ClockSignal Slave Clock input, typically 25MHz, which sets the master transmit/receive rate.
eth 2.4.19 VirtualEthernet protocol Master Ethernet port.
intr 2.7.2 Signal protocol Master Interrupt signal.
pvbus PVBus Slave Slave port for register access.
state ValueState_64 Master State port to retrieve state of host bridge
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