3.7.3 Base_PowerController

Base Platforms Power Controller. This model is written in LISA+.

Base_PowerController contains the following CADI targets:

  • Base_PowerController

Base_PowerController contains the following MTI components:

Table 3-215 Ports

Name Protocol Type Description
cpuporeset[16] 2.7.2 Signal protocol Master -
dbgnopwrdwn[16] 2.7.2 Signal protocol Slave -
l2reset[4] 2.7.2 Signal protocol Master -
pchannel_m[16] 2.5.1 PChannel protocol Master -
pvbus_s PVBus Slave -
standbywfi[16] 2.7.2 Signal protocol Slave -
standbywfil2[4] 2.7.2 Signal protocol Slave -
system_reset 2.7.2 Signal protocol Master -
system_reset_req 2.7.2 Signal protocol Slave -
wakerequest[16] 2.7.2 Signal protocol Slave -

Table 3-216 Parameters for Base_PowerController

Name Type Default value Description
Affinity-shifted bool 0x0 Are the CPU affinities shifted ? true if it is one of the APACHE cores otherwise false
CPU-affinities string "0.0.0.0" Definition of which cores are attached to the control pins, as a comma separated list of affinity dotted quads
CPU-available-mask int -0x1 One bit per entry in CPU-affinities list, set zero if a CPU is wired up but actually not available
startup string "0.0.0.*" Comma-separated list of cores (wildcards allowed) to be powered up at startup or system reset
use_pchannel_for_threads bool 0x0 Set this to true if the pchannel is connected to cpus with thread support.
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