3.5.8 Mali_G51

Arm® Mali™-G51 GPU. This model is written in C++.

Mali_G51 contains the following CADI targets:

  • Mali_G51

Mali_G51 contains the following MTI components:

Limitations

The model has the following limitations:

  • It does not support ARMv8-style page tables.
  • It does not execute GPU shader programs.
  • It does not validate all register values or job descriptors.

Mali™ performance counters

This model outputs values for all Mali PMU hardware counters. These values are not meaningful. Their purpose is to enable you to use the model early in the development process to check that your system is correctly configured to support performance analysis tools, for instance Streamline.

The counter is a 32-bit bitfield, with the following bit assignments:

[31:28]
Identifies which Mali GPU instance generated this value, typically zero for a system with a single GPU.
[27:24]
Identifies which hardware block is the source of the counter. It can have one of the following values:
0Job manager.
1Tiler.
2L2Cache/Memory system.
3+Shader core.
[23:16]
The counter number within the block.
[15:0]

Sawtooth counter that counts from 0 to 0xffff and then resets to 0. This value ensures that consecutive captures show different values and allows you to check that counter values are changing over time.

Note:

  • These counter values might change in future versions.
  • The model always generates counter values, even if the GPU is idle.
  • Streamline does not display the precise values that the model outputs because it needs to correct them for sampling frequency and other profiling effects. However, their size relative to each other is correct. For example, counters from the job manager are always smaller than those from the memory system.

Table 3-200 Ports

Name Protocol Type Description
gpu_reset 2.7.2 Signal protocol Slave Resets the GPU at the input Set. The available inputs are Set and Clear.
irq_gpu 2.7.2 Signal protocol Master The interrupt signal generated from the GPU.
irq_job 2.7.2 Signal protocol Master The interrupt signal generated from the Job Manager on the GPU.
irq_mmu 2.7.2 Signal protocol Master The interrupt signal generated from the MMU on the GPU.
prot_mode_m0 2.7.2 Signal protocol Master Indicates the current state of the GPU. When it outputs: Set: The GPU is in protected mode. Clear: The GPU is in normal mode. Typically, connect this signal to the LabellerForGPUProtMode component. This enables the labeller to add a Non-Secure Access ID to the outgoing transaction on the labeller's pvbus_m port.
pvbus_m PVBus Master The interface for the GPU to access external memory.
pvbus_s PVBus Slave The interface for the CPU to access the GPU registers.
Non-ConfidentialPDF file icon PDF version100964_1161_00_en
Copyright © 2014–2019 Arm Limited or its affiliates. All rights reserved.