4.86 MMU_400_BASE - trace

This section describes the trace sources.

aarch64_AddressSizeFault_base_address_out_of_range

An AArch64 context got an AddressSizeFault as the base address of the TTBR used is out of range. Fields:

CPAMax unsigned int
Configured PAMax.
PAMax unsigned int
Actual PAMax.
context_bank unsigned int
context_bank.
stage unsigned int
Stage.

aarch64_AddressSizeFault_in_final_block_address_trace

An AArch64 context got an AddressSizeFault in the final block descriptor. Fields:

CPAMax unsigned int
Configured PAMax.
PAMax unsigned int
Actual PAMax.
context_bank unsigned int
context_bank.
output_address unsigned int
Output address from stage.
stage unsigned int
Stage.

aarch64_AddressSizeFault_in_table_descriptor

An AArch64 context got an AddressSizeFault as a descriptor encoded a page and the table base address described was out of range. Fields:

CPAMax unsigned int
Configured PAMax.
PAMax unsigned int
Actual PAMax.
context_bank unsigned int
context_bank.
ipa_address unsigned int
IPA of descriptor.
ns bool
Descriptor address is non-secure.
pa_address unsigned int
PA of descriptor.
stage unsigned int
Stage.

aarch64_TranslationFault_as_block_too_large

The AArch64 block described by a descriptor is too large. Fields:

context_bank unsigned int
context_bank.
level unsigned int
level.
stage unsigned int
stage.

aarch64_TranslationFault_input_address_out_of_range

An AArch64 context received an address which was outside of the programmed TxSZ. Fields:

context_bank unsigned int
context_bank.
input_address unsigned int
Input address to stage.
ns bool
Security state of context bank.
stage unsigned int
Stage.

aarch64_TranslationFault_st2_starting_level_and_tsize_inconsistent

An AArch64 context got a TranslationFault as the specified starting level and TxSZ field are inconsistent. Fields:

context_bank unsigned int
context_bank.
stage unsigned int
Stage.

add_ns_context_fault

A context fault occurred and this is the record it wishes to generate. Fields:

SMMU_CBFRSYNRAn unsigned int
SMMU_CBFRSYNRAn value that it wishes to write.
SMMU_CBn_FAR unsigned int
SMMU_CBn_FAR value that it wishes to write.
SMMU_CBn_FSR unsigned int
SMMU_CBn_FSR value that it wishes to write.
SMMU_CBn_FSYNR0 unsigned int
SMMU_CBn_FSYNR0 value that it wishes to write.
SMMU_CBn_FSYNR1 unsigned int
SMMU_CBn_FSYNR1 value that it wishes to write.
SMMU_CBn_IPAFAR unsigned int
(SMMUv2 only) SMMU_CBn_IPAFAR value that it wishes to write. The value is UNKNOWN if this is a stage 1 context.
context_bank unsigned int
Context bank.
going_to_be_lost bool
This fault record is going to be lost as there is already an unhandled fault record.

add_ns_global_fault

Attempt to raise a Non-Secure global fault. Fields:

SMMU_GFAR unsigned int
The fault address that we are attempting to record.
SMMU_GFSR unsigned int
The bits that we are attempting to set in the SMMU_GFSR.
SMMU_GFSYNR0 unsigned int
The syndrome we are attempting to record.
SMMU_GFSYNR1 unsigned int
The syndrome we are attempting to record.
going_to_be_lost bool
This fault record is going to be lost as there is already an unhandled fault record.

add_s_context_fault

A context fault occurred and this is the record it wishes to generate. Fields:

SMMU_CBFRSYNRAn unsigned int
SMMU_CBFRSYNRAn value that it wishes to write.
SMMU_CBn_FAR unsigned int
SMMU_CBn_FAR value that it wishes to write.
SMMU_CBn_FSR unsigned int
SMMU_CBn_FSR value that it wishes to write.
SMMU_CBn_FSYNR0 unsigned int
SMMU_CBn_FSYNR0 value that it wishes to write.
SMMU_CBn_FSYNR1 unsigned int
SMMU_CBn_FSYNR1 value that it wishes to write.
SMMU_CBn_IPAFAR unsigned int
(SMMUv2) SMMU_CBn_IPAFAR value that it wishes to read. This becomes UNKNOWN as this is a secure bank.
context_bank unsigned int
Context bank.
going_to_be_lost bool
This fault record is going to be lost as there is already an unhandled fault record.

add_s_global_fault

Attempt to raise a Secure global fault. Fields:

SMMU_SGFAR unsigned int
The fault address that we are attempting to record.
SMMU_SGFSR unsigned int
The bits that we are attempting to set in the SMMU_SGFSR.
SMMU_SGFSYNR0 unsigned int
The syndrome we are attempting to record.
SMMU_SGFSYNR1 unsigned int
The syndrome we are attempting to record.
going_to_be_lost bool
This fault record is going to be lost as there is already an unhandled fault record.

ats_cb_atsr_read

A context bank Address Translation Status Register read occurred (Writes are reported through ats_cb_operation_doesnt_exist_trace). Fields:

ACTIVE bool
The ACTIVE bit returned.
context_id unsigned int
Context bank ID.
is_debug bool
The access was a debug access.

ats_cb_operation_doesnt_exist

An attempt was made to use a Context Bank Address Translation Operation that didn't exist for some reason. Fields:

context_id unsigned int
Context bank ID.
desc string
Description of why it doesn't exist.

ats_cb_operation_queued

A new Context Bank Address Translation Operation was queued. Fields:

VA unsigned int
Virtual Address.
ats_is_privileged bool
The ATS operation is asking for a 'privileged' access.
ats_is_read bool
The ATS operation is asking for a 'read' access.
context_id unsigned int
Context bank ID.
is_debug bool
Is for a debug request.

ats_cb_operation_received_while_ats_in_progress

Another Context Bank Address Translation operation was received whilst one was currently in progress. This is UNPREDICTABLE. Fields:

context_id unsigned int
Context bank ID.
desc string
Description of new ATS operation.

ats_global_atsr_read

A Global Address Translation Status Register read occurred (Writes are reported through ats_cb_operation_doesnt_exist_trace). Fields:

ACTIVE bool
The ACTIVE bit returned.
is_debug bool
The access was a debug access.
which enum
Which global ATSR register?

ats_global_operation_doesnt_exist

An attempt was made to use a Context Bank Address Translation Operation that didn't exist for some reason. Fields:

desc string
Description of why it doesn't exist.
is_non_secure enum
Is the operation non-secure.

ats_global_operation_queued

A new Context Bank Address Translation Operation was queued. Fields:

VA unsigned int
Virtual Address.
ats_is_privileged bool
The ATS operation is asking for a 'privileged' access.
ats_is_read bool
The ATS operation is asking for a 'read' access.
context_id unsigned int
Context bank ID.
is_debug bool
Is for a debug request.
is_non_secure enum
Is the operation non-secure.
is_s12 bool
Is a stage 1 and stage 2 translation.

ats_global_operation_received_while_ats_in_progress

Another Global Address Translation operation was received whilst one was currently in progress. This is UNPREDICTABLE. Fields:

context_id unsigned int
Context bank ID of new operation.
desc string
Description of new ATS operation.
is_non_secure enum
Is the operation non-secure.

ats_op_started

A queued address translation operation has started. Fields:

VA unsigned int
Input virtual address.
context_bank unsigned int
Context bank if which == 'context_bank'.
is_debug bool
The operation is a debug ATS command.
is_privileged bool
Is a privileged operation.
is_read bool
Is a read operation.
is_s12 bool
Is for a stage 1 and 2 translation.
which enum
Which group of operations?

cfg_cttw

The cfg_cttw signal level that indicates that the SoC support coherent page walks. Fields:

value bool
The signal level.

cfg_flt_irpt

Configuration Fault Interrupt. Fields:

asserted bool
The signal is asserted.
is_non_secure bool
cfg_flt_irpt_ns or cfg_flt_irpt_s.

changed_PAGESIZE

The PAGESIZE has been told to change. Fields:

is_64KiB bool
The PAGESIZE is 64 KiB.

changing_security_state_of_context_bank

The specified bank has changed its security state. Fields:

context_bank unsigned int
Context bank number.
now_is_non_secure bool
The context bank is now non-secure.
prev_is_non_secure bool
Prior to this change in the SMMU_SCR1.NSNUMCBO then the bank was non-secure.

cmo_permission_fault

A Cache Maintenance Operation (CMO) generated a permission fault. Fields:

abort_returned_to_device bool
An abort is returned to the device.
cmo enum
Cache Maintenance Operation.
context_id unsigned int
Context ID that receives the fault.
input_address unsigned int
The address of the CMO.

cmo_permission_model_being_applied

The cache maintenance operation permission model is being applied. Fields:

aarch64 bool
Is the initial context bank aarch64?
fault_action enum
Whether there is a fault or not.
incoming_cmo_operation enum
The CMO operation.
instruction bool
Is the CMO instruction?
outgoing_cmo_operation enum
The CMO operation.
privileged bool
Is the CMO privileged?
stage1_perms enum
The permissions at stage 1.
stage2_perms enum
The permissions at stage 1.

comb_irpt

Combined interrupt signal. This is the OR of all of the non-secure interrupt signals. Fields:

asserted bool
The signal is asserted.
is_non_secure bool
Is the comb_irpt_ns signal or the comb_irpt_s signal.

configuration_access_fault_unimplemented_stream_mapping_register_group

This occurs when a configuration transaction attempts to access a stream mapping register group that doesn't exist and if the implementation treats this as a Configuration Access Fault. Fields:

address unsigned int
Address that was used.
group_number unsigned int
Group number if it were to exist/be accessible.
is_non_secure bool
Is the configuration access non-secure?
is_read bool
Is the configuration access a read?

context_bank_commentary

These messages are verbose commentary about what the context bank is doing. Fields:

output string
The stream output.

context_bank_mmu_off_stage1

This is the transformation applied by the stage 1 SMMU_CBn_SCTLR. Fields:

SMMU_CBn_SCTLR unsigned int
Value of the SMMU_CBn_SCTLR used.
context_id unsigned int
Context bank id the transaction has been mapped to.
trans_id unsigned int
Transaction ID.

context_bank_mmu_off_stage2

This is the transformation applied by the stage 2 SMMU_CBn_SCTLR. Fields:

SMMU_CBn_SCTLR unsigned int
Value of the SMMU_CBn_SCTLR used.
context_id unsigned int
Context bank id the transaction has been mapped to.
trans_id unsigned int
Transaction ID.

ctx_irpt_ns

Context Interrupt, this can only ever be non-secure. Fields:

asserted bool
The signal is asserted.

debug

This is the textual output of the debug messages of the SMMU model, this need not necessarily make much sense to the user, but is useful for sending to the model writers when reporting bugs. Fields:

output string
The stream output.

denied_access_due_to_imp_def_reason

The register access was denied because of some IMPLEMENTATION DEFINED reason due to the transaction attributes. Fields:

address unsigned int
Address of register access.
desc string
Description of register.

denied_access_due_to_smmu_scr1_gasrae

The register access was denied because SMMU_SCR1.GASRAE has locked down the register. Fields:

address unsigned int
Address of register access.

dvm_tlbinvalidate_complete

The DVM TLB Invalidate message completed.

dvm_tlbinvalidate_received

A DVM message for a TLB Invalidate has been received. Fields:

address unsigned int
The VA or IPA to use if match_address.
asid unsigned int
The ASID to match if match_asid.
by_ipa bool
The operation is for an IPA operation if match_address.
ignored enum
The DVM message was ignored.
last_level bool
The operation is for last level if supported.
match_address bool
Match the address field.
match_asid bool
Match the asid field.
match_vmid bool
Match the vmid field.
prot enum
The protection level for which this TLB Invalidate will operate on.
security_world enum
The security world that this will apply to.
stage1_only bool
The operation is for stage 1 only if supported.
vmid unsigned int
The VMID to match if match_vmid.

end_stall_transaction

Indicates a transaction unstalling. Fields:

context_id unsigned int
The context id that we are stalling against.
trans_id unsigned int
Transaction id of replaying transaction.
unstall_state enum
Describes why we unstalled. If we are head of line then we are either replay/terminate, otherwise we will be not be.

error

These messages are about activity occurring on the SMMU that is considered an error. Fields:

output string
The stream output.

error_contiguous_bit_is_bad

The contiguous bit is inconsistent with the descriptor. Fields:

B_mask unsigned int
The mask of the address that is zapped if we were to use the contiguous bit.
aarch64_contig_bit_too_high bool
AArch64 claims that the contig bit can't be set for this particular set of start levels and input address size.
input_address unsigned int
The input address that will be combined with the output address.
ln2_size_in_bytes_of_region_if_contiguous unsigned int
The number of address bits that form the 'offset' within the contiguous region.
out_of_range_of_input bool
The range mapped by a contiguous bit being on is larger than the input range for this stage.
output_address unsigned int
The output address as contained in the descriptor.
output_address_if_contig_bit_uses_input_address unsigned int
Output address if contig bit was fully taken (maximally sized region) and those bits came from the input address.
output_address_inconsistent bool
The output address in the descriptor is inconsistent with its position in the table.
stage_and_level unsigned int
Top 8 bits are the stage, bottom 8 bits are level.

error_invalid_smmu_cbar

A SMMU_CBAR has been encountered for a secure stream that is not of the Stage 1 with Stage 2 bypass form. Fields:

SMMU_CBARn unsigned int
The corresponding SMMU_CBARn for the context.
action enum
Action taken.
context_id unsigned int
Context ID.
trans_id unsigned int
Transaction id.

error_tlb_entries_overlap

A TLB entry was attempted to be inserted into the TLB and was determined that it overlaps an existing entry. This check is not perfect but will catch simple errors. Fields:

end_address_of_new_entry unsigned int
End address of new entry.
end_address_of_old_entry unsigned int
End address of old entry.
index_of_new_entry unsigned int
Index of new entry.
index_of_old_entry unsigned int
Index of old entry.
start_address_of_new_entry unsigned int
Start address of new entry.
start_address_of_old_entry unsigned int
Start address of old entry.

extended_attributes_for_stage

This gives the attributes that a particular stage gives prior to being applied to the incoming attributes. Fields:

inner enum
Inner cacheability.
ns bool
NS/S security state.
outer enum
Outer cacheability.
racfg enum
RACFG from descriptor (if exists).
shareability enum
Shareability.
stage unsigned int
Stage that this record is for.
trans_id unsigned int
Transaction ID this is for.
wacfg enum
WACFG from descriptor (if exists).

glbl_flt_irpt

Global Fault Interrupt. Fields:

asserted bool
The signal is asserted.
is_non_secure bool
glbl_flt_irpt_ns or glbl_flt_irpt_s.

imp_def_non_SMMU_CBn_RESUME_register_access_transaction_forces_replay

There is an IMP DEF option to replay stalled transactions in affected banks. This records that the implementation has made use of this option. Fields:

context_id unsigned int
Context ID of affected bank.
why enum
Why did this replay occur?

implementation_postprocess

This describes the non-architectural transformation that the implementation makes. Fields:

end_adomain enum
End adomain value.
end_inner_acache enum
End inner acache value.
end_outer_acache enum
End outer acache value.
is_read bool
Is a read transaction.
start_adomain enum
Start adomain value.
start_inner_acache enum
Start inner acache value.
start_outer_acache enum
Start outer acache value.

info

These are information messages about what is happening in the SMMU. Fields:

output string
The stream output.

invalid_address_range

An input or output address range check failed. Input address range checks are reported as TranslationFault, output ones as AddressSizeFault. Fields:

context_bank unsigned int
Context bank.
offending_address unsigned int
The address that failed the address check.
why enum
The reason why the address was invalid.

ld_access_fault

An Access Fault occurred. Fields:

context_bank unsigned int
Context bank.
input_address unsigned int
The input address used for this descriptor.
is_non_secure bool
Is the input address non-secure?
level unsigned int
Level of walk.
stage unsigned int
Stage of walk.

ld_descriptor_fetch_failed

Long Descriptor AArch32 or AArch64, level 'n' descriptor fetch failed. Fields:

context_bank unsigned int
Context bank.
ipa_address unsigned int
IPA of the descriptor address.
is_non_secure bool
Is the page walk and input addresses non-secure?
level unsigned int
Level of walk.
pa_address unsigned int
PA of the descriptor address.
stage unsigned int
Stage of walk.

ld_descriptor_invalid

Long Descriptor AArch32 or AArch64 encodes an invalid entry. Fields:

context_bank unsigned int
Context bank.
ipa_address unsigned int
IPA of the descriptor address.
level unsigned int
Level of walk.
pa_address unsigned int
PA of the descriptor address.
ssd_ns bool
Is the transaction classified as non-secure.
stage unsigned int
Stage of walk.

ld_hyp_mode_address_out_of_range

A hypervisor input address is out of range of T0SZ. Fields:

context_bank unsigned int
The context bank.
input_address unsigned int
The VA input address used for this descriptor.
is_non_secure bool
Is this for the Non-secure side?

ld_ipa_out_of_range

A stage 2 context bank was given an address that didn't match T0SZ. Fields:

context_bank unsigned int
The context bank.
input_address_ipa unsigned int
The IPA input address used for this descriptor.
is_non_secure bool
Is this for the Non-secure side?

ld_ipa_out_of_range_for_st1ptw_st2_mmu_off

(SMMUv2) The stage 2 context (nested with MMU off or bypass) for a stage 1 translation had an address that was out of the allowed range. Fields:

context_bank unsigned int
The context bank.
input_address_ipa unsigned int
The IPA input address used for this descriptor.
is_non_secure bool
Is this for the Non-secure side?

ld_last_level_descriptor_does_not_encode_a_page

Long Descriptor, last level descriptor must encode a page but didn't. Fields:

context_bank unsigned int
Context bank.
ipa_address unsigned int
IPA of the descriptor address.
level unsigned int
Level of walk.
pa_address unsigned int
PA of the descriptor address.
ssd_ns bool
Is the transaction classified as non-secure?
stage unsigned int
Stage of walk.

ld_misprogramming_fault_trace

A misprogramming occurred that the implementation faulted. Fields:

context_bank unsigned int
Context bank.
input_address unsigned int
Input address.
stage unsigned int
Stage.
why enum
Why the fault occurred.

ld_st2_produced_any_device_memory_for_st1ptw

A stage 2 translation process for a stage 1 page walk address produce a any-device memory type. Fields:

context_bank unsigned int
Context bank.
input_address unsigned int
The input address used for this descriptor.
level unsigned int
Level of walk.

ld_st2_s1ptw_has_no_access_rights

A stage 2 translation process for a stage 1 page walk address produce a permission fault. Fields:

context_bank unsigned int
Context bank.
input_address unsigned int
The input address used for this descriptor.
level unsigned int
Level of walk.

ld_stage1_non_hyp_no_ttbr_match

A stage 1 non-hyp entry failed to match TTBR0 or TTBR1. Fields:

context_bank unsigned int
The context bank.
input_address unsigned int
The input address used.
is_non_secure bool
Is this for the Non-secure side?

ld_walk_process_is_disabled

A L1 or L2 short descriptor access flag has disabled access for this (super-)section/page. Fields:

context_bank unsigned int
The context bank.
input_address unsigned int
The input address used.
is_non_secure bool
Is this for the Non-secure side?
stage unsigned int
Which change this corresponds to.
ttbr_id unsigned int
Which TTBR we are using (is 0 for a stage 2).

non_PTW_external_fault_recorded

A non Page Table Walk access was recorded when a translated transaction went downstream, but the downstream system aborted it. This is recorded as an asynchronous fault. In the model, we can provide more information about the faulting transaction. Fields:

downstream_address unsigned int
The downstream address.
downstream_ns enum
The downstream NS state. This is not the SSD.
is_read enum
Is the transaction a read?
result_reported_upstream enum
The result that is reported upstream.
sGFSYNR0 unsigned int
The value of sGFSYNR0 that will attempt to be recorded (all 1s mean it will not be updated).
sGFSYNR1 unsigned int
The value of sGFSYNR1 that will attempt to be recorded (all 1s mean it will not be updated).
smmu_scr1_gefro bool
The value of SMMU_SCR1.GEFRO.
smmu_xcr0_gfre bool
The appropriate SMMU_sCR0.GFRE bit. If this is 0 then it squash the downstream abort.
ssd_ns enum
SSD.
upstream_address unsigned int
The upstream address.
upstream_ns enum
The upstream NS state. This is not the SSD.

post_s2crn_attributes

The attributes after the SMMU_S2CRn transformation has been applied. Fields:

adomain enum
The actual attributes of the access that was used, after IMP DEF mangling.
aprot enum
The actual attributes of the access that was used, after IMP DEF mangling.
inner_cache enum
The actual attributes of the access that was used, after IMP DEF mangling.
inner_transient bool
Is the transaction marked with the transient hint?
outer_cache enum
The actual attributes of the access that was used, after IMP DEF mangling.
outer_transient bool
Is the transaction marked with the transient hint?
trans_id unsigned int
Transaction id.
v8_dev_gathering bool
Is the transaction marked with the V8 Device Gathering property?
v8_dev_reordering bool
Is the transaction marked with the V8 Device Reordering property?

ptw_read

Page Table Walk (read). This is the physical access that the SMMU is making. Fields:

adomain enum
The actual attributes of the access that was used, after IMP DEF mangling.
aprot enum
The actual attributes of the access that was used, after IMP DEF mangling.
auser unsigned int
The AUSER fields.
data unsigned int
The data read in little-endian format.
hyp bool
Current mode is hyp.
inner_cache enum
The actual attributes of the access that was used, after IMP DEF mangling.
input_address unsigned int
Input address this lookup is for.
ns bool
This is for SSD Non-secure.
outer_cache enum
The actual attributes of the access that was used, after IMP DEF mangling.
pa_address unsigned int
Physical address.
result enum
The PTW result.
st2_st1_context_banks unsigned int
The stage 1 and 2 context bank that this walk is for (if there is one, otherwise 0xFF). Stage 1 is the lowest byte, stage 2 the highest.
stage_and_level unsigned int
Stage and level that this walk is for. Top byte is stage, bottom is level.
trans_id unsigned int
Transaction id.

ptw_read_st1_invalid_long_descriptor

Page Table Walk (read). The descriptor that the PTW fetched is invalid. Fields:

hyp bool
Current mode is hyp.
input_address unsigned int
Input address this lookup is for.
level unsigned int
The page table level this walk is for.
ns bool
This is for SSD Non-secure.
pa_address unsigned int
Physical address.
st1_context_bank unsigned int
The stage 1 context bank that this walk is for (if there is one, otherwise 0xFF).
st2_context_bank unsigned int
The stage 2 context bank that this walk is for (if there is one, otherwise 0xFF).
trans_id unsigned int
Transaction id.

ptw_read_st1_leaf_long_descriptor

Page Table Walk (read). The descriptor that the PTW fetched is a block or page and this is the decode. Fields:

AF bool
Access Flag.
AP21 enum
The access permissions.
AttrIndx210 unsigned int
The attribute index into the MAIR0/1.
NS bool
The encoding is for non-secure if this is a secure fetch.
PXN bool
Privileged eXecute Never.
SH10 enum
The shareability.
XN bool
eXecute Never.
contiguous bool
Contiguous hint.
hyp bool
Current mode is hyp.
input_address unsigned int
Input address this lookup is for.
level unsigned int
The page table level this walk is for.
mair unsigned int
The MAIRn encoding attribute.
nG bool
not Global.
ns bool
The agent is Non-Secure.
output_address unsigned int
Output address.
pa_address unsigned int
Physical address.
st1_context_bank unsigned int
The stage 1 context bank that this walk is for (if there is one, otherwise 0xFF).
st2_context_bank unsigned int
The stage 2 context bank that this walk is for (if there is one, otherwise 0xFF).
trans_id unsigned int
Transaction id.

ptw_read_st1_table_long_descriptor

Page Table Walk (read). The descriptor that the PTW fetched is a Table, this decodes the fields. Fields:

APTable enum
Remove permissions independently of subsequent descriptors.
NSTable bool
The next level table descriptor is forced to non-secure.
PXNTable bool
Force PXN independently of subsequent descriptors.
TableAddress unsigned int
Address of the next table.
XNTable bool
Force XN independently of subsequent descriptors.
hyp bool
Current mode is hyp.
input_address unsigned int
Input address this lookup is for.
level unsigned int
The page table level this walk is for.
ns bool
This is for SSD Non-secure.
pa_address unsigned int
Physical address.
st1_context_bank unsigned int
The stage 1 context bank that this walk is for (if there is one, otherwise 0xFF).
st2_context_bank unsigned int
The stage 2 context bank that this walk is for (if there is one, otherwise 0xFF).
trans_id unsigned int
Transaction id.

ptw_read_st1_v7s_fault_descriptor

Page Table Walk (read). The descriptor encodes a fault descriptor. Fields:

level unsigned int
The level of the page table.
trans_id unsigned int
Transaction id.

ptw_read_st1_v7s_large_page_descriptor

Page Table Walk (read). The descriptor encodes a large page descriptor. Fields:

AP210 unsigned int
AP[2:0].
S bool
Shareable.
TEX210CB unsigned int
{TEX[2:0],C,B}.
XN bool
eXecute Never.
large_page_base_address unsigned int
Base address of the large page.
nG bool
not Global.
trans_id unsigned int
Transaction id.

ptw_read_st1_v7s_page_table_descriptor

Page Table Walk (read). The descriptor encodes a page table descriptor pointing to an L2 table. Fields:

NS bool
Encodes a non-secure entry.
PXN bool
Privileged eXecute Never.
domain unsigned int
Domain.
l2_table_address unsigned int
L2 page table address.
trans_id unsigned int
Transaction id.

ptw_read_st1_v7s_section_descriptor

Page Table Walk (read). The descriptor encodes a section descriptor. Fields:

AP210 unsigned int
AP[2:0].
NS bool
Encodes a non-secure entry.
PXN bool
Privileged eXecute Never.
S bool
Shareable.
TEX210CB unsigned int
{TEX[2:0],C,B}.
XN bool
eXecute Never.
domain unsigned int
Domain.
nG bool
not Global.
section_base_address unsigned int
Base address of section.
trans_id unsigned int
Transaction id.

ptw_read_st1_v7s_small_page_descriptor

Page Table Walk (read). The descriptor encodes a small page descriptor. Fields:

AP210 unsigned int
AP[2:0].
S bool
Shareable.
TEX210CB unsigned int
{TEX[2:0],C,B}.
XN bool
eXecute Never.
nG bool
not Global.
small_page_base_address unsigned int
Base address of the small page.
trans_id unsigned int
Transaction id.

ptw_read_st1_v7s_super_section_descriptor

Page Table Walk (read). The descriptor encodes a section descriptor. Fields:

AP210 unsigned int
AP[2:0].
NS bool
Encodes a non-secure entry.
PXN bool
Privileged eXecute Never.
S bool
Shareable.
TEX210CB unsigned int
{TEX[2:0],C,B}.
XN bool
eXecute Never.
nG bool
not Global.
super_section_base_address unsigned int
Base address of the super section.
trans_id unsigned int
Transaction id.

ptw_read_st2_invalid_descriptor

Page Table Walk (read). The descriptor that the PTW fetched is invalid. Fields:

hyp bool
Current mode is hyp.
input_address unsigned int
Input address this lookup is for.
level unsigned int
The page table level this walk is for.
ns bool
This is for SSD Non-secure.
pa_address unsigned int
Physical address.
st1_context_bank unsigned int
The stage 1 context bank that this walk is for (if there is one, otherwise 0xFF).
st2_context_bank unsigned int
The stage 2 context bank that this walk is for (if there is one, otherwise 0xFF).
trans_id unsigned int
Transaction id.

ptw_read_st2_leaf_descriptor

Page Table Walk (read). The descriptor that the PTW fetched is a block or page and this is the decode. Fields:

AF bool
Access Flag.
HAP21 enum
The access permissions.
MemAttr3_0 enum
The memory attributes.
RACFG enum
The extra SMMU RACFG field.
SH10 enum
The shareability.
WACFG enum
The extra SMMU WACFG field.
XN bool
eXecute Never.
contiguous bool
Contiguous hint.
hyp bool
Current mode is hyp.
input_address unsigned int
Input address this lookup is for.
level unsigned int
The page table level this walk is for.
ns bool
This is for SSD Non-secure.
output_address unsigned int
Output address.
pa_address unsigned int
Physical address.
st1_context_bank unsigned int
The stage 1 context bank that this walk is for (if there is one, otherwise 0xFF).
st2_context_bank unsigned int
The stage 2 context bank that this walk is for (if there is one, otherwise 0xFF).
trans_id unsigned int
Transaction id.

ptw_read_st2_table_descriptor

Page Table Walk (read). The descriptor that the PTW fetched is a Table, this decodes the fields. Fields:

APTable enum
Remove permissions independently of subsequent descriptors.
NSTable bool
The next level table descriptor is forced to non-secure.
PXNTable bool
Force PXN independently of subsequent descriptors.
TableAddress unsigned int
Address of the next table.
XNTable bool
Force XN independently of subsequent descriptors.
hyp bool
Current mode is hyp.
input_address unsigned int
Input address this lookup is for.
level unsigned int
The page table level this walk is for.
ns bool
This is for SSD Non-secure.
pa_address unsigned int
Physical address.
st1_context_bank unsigned int
The stage 1 context bank that this walk is for (if there is one, otherwise 0xFF).
st2_context_bank unsigned int
The stage 2 context bank that this walk is for (if there is one, otherwise 0xFF).
trans_id unsigned int
Transaction id.

raw_want_to_change_context_interrupt

This represents a context's bank intent to want to change an interrupt pin. However, this doesn't take into account the accessibility of the bank, nor if other banks are driving the pin. Fields:

accessible bool
Is the interrupt ID accessible to this context bank?
asserted bool
Is this context bank attempting to assert the interrupt?
context_bank unsigned int
Context bank attempting to change the interrupt pin.
interrupt_id unsigned int
The interrupt ID it is attempting to change.

register_disallowed_read_string

A text representation of the read of a register that was disallowed. Fields:

out string
The text description of the register value read

register_disallowed_write_string

A text representation of the write of a register write that was disallowed. Fields:

in string
The text description of the register value written

register_read

Read of the register file. Fields:

address unsigned int
The address of the register.
context_id unsigned int
Context id bank (or 0xFF if not a context bank)
ln2_width enum
The log2 width of the access
ns enum
The security state of the transaction addressing the register
register_trans_id unsigned int
Register transaction ID (if top bit set then a debug transaction)
result enum
The result of the access
value unsigned int
The byte-stream of all the data (little-endian)

register_read_reserved

A text representation of an access to a register address that is reserved. Fields:

in string
The text description of the register value

register_read_string

A text representation of the read of a register. Fields:

out string
The text description of the register value read

register_write

Write to the register file. Fields:

address unsigned int
The address of the register.
context_id unsigned int
Context id bank (or 0xFF if not a context bank)
ln2_width enum
The log2 width of the access
ns enum
The security state of the transaction addressing the register
register_trans_id unsigned int
Register transaction ID (if top bit set then a debug transaction)
result enum
The result of the access
value unsigned int
The byte-stream of all the data (little-endian)

register_write_reserved

A text representation of an access to a register address that is reserved. Fields:

in string
The text description of the register value

register_write_string

A text representation of the write of a register. Fields:

in string
The text description of the register value written

reset

A reset has been received by the SMMU. Fields:

asserted bool
True if reset is asserted.

smmu_faulting_transaction

This is a trace of transaction that are not expected to fault. This does not include those transaction that are faulting by stage 2 or where the access flag or permission model is not allowing the transaction. Fields:

context_id unsigned int
The context id of the transaction used, if we failed to immediately hit in the TLB.
input_address unsigned int
The input address of the transaction group.
mapped_attributes unsigned int
The mapped attributes of the transaction.
original_attributes unsigned int
The original unmapped attributes of the transaction.
output_address unsigned int
The output address of the transaction group.
ssd_index unsigned int
The Security State Determination Index if applicable.
ssd_ns enum
The Security State Determination of the transaction.
state enum
The state of the transaction.
stream_id unsigned int
The stream id of the transaction
tbu unsigned int
Translation Buffer Unit number.
tlb_entry_index_st1 unsigned int
If this was mapped by a TLB entry index then this is the one used for the stage 1 translation.
tlb_entry_index_st2 unsigned int
If this was mapped by a TLB entry index then this is the one used for the stage 2 translation.
trans_id unsigned int
Transaction id.
type_of_transaction enum
The type of transaction.

smmu_final_transaction

This is a trace of the SMMU transaction after it has been fully remapped. Fields:

context_id unsigned int
The context id of the transaction used, if we failed to immediately hit in the TLB.
input_address unsigned int
The input address of the transaction group.
mapped_attributes unsigned int
The mapped attributes of the transaction.
original_attributes unsigned int
The original unmapped attributes of the transaction.
output_address unsigned int
The output address of the transaction group.
ssd_index unsigned int
The Security State Determination Index if applicable.
ssd_ns enum
The Security State Determination of the transaction.
state enum
The state of the transaction.
stream_id unsigned int
The stream id of the transaction
tbu unsigned int
Translation Buffer Unit number.
tlb_entry_index_st1 unsigned int
If this was mapped by a TLB entry index then this is the one used for the stage 1 translation.
tlb_entry_index_st2 unsigned int
If this was mapped by a TLB entry index then this is the one used for the stage 2 translation.
trans_id unsigned int
Transaction id.
type_of_transaction enum
The type of transaction.

smmu_initial_transaction

This is the initial transaction group request to remap. This represents a bundle of transactions with the same attributes but different addresses within a certain range around the address. Fields:

input_address unsigned int
The input address of the transaction group.
kind_addressed enum
The kind of transaction this represents if it is an addressed transaction
original_attributes unsigned int
The original unmapped attributes of the transaction.
ssd_index unsigned int
The Security State Determination Index if applicable.
ssd_ns enum
The Security State Determination of the transaction.
stream_id unsigned int
The stream id of the transaction.
tbu unsigned int
Translation Buffer Unit number.
trans_id unsigned int
Transaction id.
type_of_transaction enum
The type of transaction.

smmu_iprt_xgirpt

This trace source records the state of the SMMU_gIrpt/SMMU_NSgIrpt pins. Fields:

asserted bool
The interrupt is now asserted.
is_non_secure bool
Identifies the pin as SMMU_NSgIrpt.

smmu_irpt_combined_context_interrupt_pin

This trace source records when there is at least one context bank in the specific world with an interrupt pin raised. Fields:

asserted bool
The interrupt is now asserted.
ns bool
Non-secure

smmu_irpt_context_interrupt_pin

This trace source records when a context bank interrupt pin changes state. Fields:

asserted bool
The interrupt is now asserted.
interrupt_pin unsigned int
Interrupt pin number.

smmu_irpt_context_interrupt_pin_drivers

This trace source records when a context bank tries to assert an interrupt. Multiple banks can drive the same pin and so long as one is driving it then it is asserted. Fields:

context_bank unsigned int
The context bank number changing its request for the pin
interrupt_pin unsigned int
Interrupt pin number.
new_count_asserting_pin unsigned int
The number of banks asserting the pin
this_context_asserting bool
The request that this context is making -- if this is true then the context bank is asserting a request

smmu_irpt_xgcfgirpt

This trace source records the state of the SMMU_gCfgIrpt/SMMU_NSgCfgIrpt pins. Fields:

asserted bool
The interrupt is now asserted.
is_non_secure bool
Identifies the pin as SMMU_NSgCfgIrpt.

smmu_st1_st2fault_transaction

This is a trace of transactions that map to stage 1 with stage 2 faulting. Fields:

context_id unsigned int
The context id of the transaction used, if we failed to immediately hit in the TLB.
input_address unsigned int
The input address of the transaction group.
mapped_attributes unsigned int
The mapped attributes of the transaction.
original_attributes unsigned int
The original unmapped attributes of the transaction.
output_address unsigned int
The output address of the transaction group.
ssd_index unsigned int
The Security State Determination Index if applicable.
ssd_ns enum
The Security State Determination of the transaction.
state enum
The state of the transaction.
stream_id unsigned int
The stream id of the transaction
tbu unsigned int
Translation Buffer Unit number.
tlb_entry_index_st1 unsigned int
If this was mapped by a TLB entry index then this is the one used for the stage 1 translation.
tlb_entry_index_st2 unsigned int
If this was mapped by a TLB entry index then this is the one used for the stage 2 translation.
trans_id unsigned int
Transaction id.
type_of_transaction enum
The type of transaction.

smrg_matched

Stream Match Register Group matched. Fields:

desc string
A textual description of the register group
n unsigned int
The SMRG that we matched against.
trans_id unsigned int
The transaction id that we are matching against.

start_ptw_read

Page Table Walk (read). This is the start of the physical access that the SMMU is making. Fields:

adomain enum
The actual attributes of the access that was used, after IMP DEF mangling.
aprot enum
The actual attributes of the access that was used, after IMP DEF mangling.
auser unsigned int
The AUSER fields.
hyp bool
Current mode is hyp.
inner_cache enum
The actual attributes of the access that was used, after IMP DEF mangling.
input_address unsigned int
Input address this lookup is for.
ns bool
This is for SSD Non-secure.
outer_cache enum
The actual attributes of the access that was used, after IMP DEF mangling.
pa_address unsigned int
Physical address.
st2_st1_context_banks unsigned int
The stage 1 and 2 context bank that this walk is for (if there is one, otherwise 0xFF). Stage 1 is the lowest byte, stage 2 the highest.
stage_and_level unsigned int
Stage and level that this walk is for. Top byte is stage, bottom is level.
trans_id unsigned int
Transaction id.

start_stall_transaction

Indicating that a transaction is stalled. Fields:

context_id unsigned int
The context id that we are stalling against.
head_of_line bool
The transaction is the head-of-line to stall -- it is the one that will pick up the value of SMMU_CBn_RESUME.
reason_for_stall enum
The state of the transaction as to why it stalled.
trans_id unsigned int
Transaction id of replaying transaction.

tlb_commentary

A commentary from the TLB about what is going on. Fields:

output string
The stream output.

tlb_entry_allocated

A TLB entry has been allocated. Fields:

index unsigned int
Index of TLB entry.
input_end_incl_address unsigned int
The end inclusive address of the input range that this matches.
input_start_address unsigned int
The start address of the input range that this matches.
output_end_incl_address unsigned int
The end inclusive address of the output range.
output_start_address unsigned int
The start address of the output range.

tlb_entry_invalidated

A TLB entry has been invalidated for some reason. Fields:

index unsigned int
Index of TLB entry.
reason enum
The reason why it was invalidated.

tlb_invalidate_command_executed

A TLB Invalidate command was executed. Fields:

address unsigned int
Address if appropriate.
asid unsigned int
ASID if appropriate.
command enum
Command queued
context_bank unsigned int
Context bank number if queue_type is 'context_bank'.
last_level bool
Last level if appropriate.
ns bool
Security world if appropriate.
queue_type enum
Queue added to
seq_id unsigned int
Sequence id for this TLB invalidate.
vmid unsigned int
VMID if appropriate.

tlb_invalidate_command_queued

A TLB Invalidate command was queued (but not synced). Fields:

address unsigned int
Address if appropriate.
asid unsigned int
ASID if appropriate.
command enum
Command queued
context_bank unsigned int
Context bank number if queue_type is 'context_bank'.
last_level bool
Last level if appropriate.
ns bool
Security world if appropriate.
queue_type enum
Queue added to
seq_id unsigned int
Sequence id for this TLB invalidate.
vmid unsigned int
VMID if appropriate.

tlb_sync

A TLB Sync command was issued. Fields:

context_bank unsigned int
Context bank number if queue_type is 'context_bank'.
ns bool
Security world
queue_type enum
Queues that will be synced

unpred_nested_st2_bank_is_not_marked_as_st2

The Stage 1 context bank is marked as Stage 1 + Stage 2 by SMMU_CBARn.TYPE; however, the Stage 2 context bank marked by SMMU_CBARn.CBNDX is not marked in it's SMMU_CBARm.TYPE as a Stage 2 context. Fields:

st1_context_bank_id unsigned int
The context bank id of the stage 1 bank.
st2_context_bank_id unsigned int
The context bank id of the stage 2 bank.

unpred_ptw_replay_asked_for_different_data

A PTW was in progress and was restarted (for some reason), but this time it asked for different data than last time. This means that the register file changed during the walk process and so the result of the translation for this transaction is unpredictable as to whether it would have seen the first or second walk data. Fields:

first_address unsigned int
The address of the first walk transaction that it performed.
first_ns bool
The NS state of the first walk transaction that it performed.
second_address unsigned int
The address that it is now walking for.
second_ns bool
The NS state that it is now walking for.
trans_id unsigned int
Transaction ID that was affected.

v7sd_access_fault

A L1 or L2 short descriptor access flag has disabled access for this (super-)section/page. Fields:

context_bank unsigned int
Context bank.
input_address unsigned int
The input address used for this descriptor.
is_non_secure bool
Is this for the Non-secure side?
level unsigned int
Level of walk.

v7sd_descriptor_faults

V7 Short Descriptor, level 'n' descriptor is marked as faulting. Fields:

context_bank unsigned int
Context bank.
input_address unsigned int
The input address used for this descriptor.
is_non_secure bool
Is this for the Non-secure side?
level unsigned int
Level of walk.

v7sd_descriptor_fetch_failed

V7 Short Descriptor, level 'n' descriptor fetch failed. Fields:

context_bank unsigned int
Context bank.
ipa_address unsigned int
IPA of the descriptor address.
is_non_secure bool
Is the page walk and input addresses non-secure?
level unsigned int
Level of walk.
pa_address unsigned int
PA of the descriptor address.

v7sd_walk_process_is_disabled

V7 Short Descriptor, walk process is disabled so producing a fault. Fields:

context_bank unsigned int
Context bank.

warning

These messages are about unusual (but not necessarily incorrect) activity occurring on the SMMU. Fields:

output string
The stream output.

warning_failed_to_clear_fsr_before_resuming

The programming model expects for the user to clear the fault in the FSR before calling SMMU_CBn_RESUME to unstall a transaction. Fields:

context_id unsigned int
Context ID of the FSR.
fault_flags_of_fsr unsigned int
Value of the fault bits of the FSR (excludes SS and the Format field).

warning_multiple_match_transaction

A transaction was encountered that multiple matched the stream id registers. Fields:

action enum
Action taken.
trans_id unsigned int
Transaction id.

warning_reg_after_doesnt_match_written_value

A write occurred that tried to set bits in a register, that for one reason or another, failed to get written. Fields:

desc string
The textual description of what happened.
Non-ConfidentialPDF file icon PDF version100964_1161_00_en
Copyright © 2014–2019 Arm Limited or its affiliates. All rights reserved.