5.15.12 Processor memory update trace

If enabled, this source traces memory update accesses caused by atomic operations.

Output syntax:

<time> <scale> {<cpu>} MU<sz>_<atomic_op> <addr> <data>

<time>

Timestamp (decimal value).

<scale>

Unit for <time>. This element gives consistency with device-specific Tarmac Trace formats.

<cpu>

Processor, or other component, that gave the instruction.

<sz>

Size of the data transfer in bytes (1, 2, 4, 8, 16).

<atomic_op>

Atomic operation performed on this memory address:

ADD
Atomic add operation.
BIC
Atomic bit clear operation.
CAS
Atomic compare and swap operation.
EOR
Atomic exclusive or operation.
ORR
Atomic bit set operation.
SMAX
Atomic signed max operation.
SMIN
Atomic signed min operation.
SWP
Atomic swap operation.
UMAX
Atomic unsigned max operation.
UMIN
Atomic unsigned min operation.
<addr>

Physical address that is used to access memory. Format according to the common address definition.

<data>

Hexadecimal value of the data transferred. The data padding is according to the size of the transfer. Data of 64 bits or more contains an underscore (_) separator every eight characters (32 bits).

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