3.10.51 PL390_GIC

Generic Interrupt Controller (PL390). This model is written in LISA+.

PL390_GIC contains the following CADI targets:

  • PL390_GIC

PL390_GIC contains the following MTI components:

PL390_GIC - about

The GIC provides support for three interrupt types:

  • Software Generated Interrupt (SGI).
  • Private Peripheral Interrupt (PPI).
  • Shared Peripheral Interrupt (SPI).

You can set:

  • Security state for an interrupt.
  • Priority state for an interrupt.
  • Enabling or disabling state for an interrupt.
  • Processors that receive an interrupt.

A processor interface consists of a pair of interfaces called pvbus_cpu and pvbus_distributor. The enable_c<n> and match_c<n> signals identify the originator of a transaction on pvbus_cpu. Similarly, enable_d<n> and match_d<n> signals identify the originator of a transaction on pvbus_distributor. <n> corresponds to the number of a processor interface.

Registers

To reduce compile time, the registers are not available by default. To activate them, uncomment one of the following statements in PL390_GIC.lisa:

// #define FEW_CADI_REGISTER
// #define ALL_CADI_REGISTER

Table 3-395 Ports

Name Protocol Type Description
cfgsdisable 2.7.2 Signal protocol Slave Set preventing write accesses to security-critical configuration registers.
enable_c[8] 2.7.6 ValueState protocol Slave Compared with masked PVBus master id to select processor interface: (master_id & enable_c<n>) == match_c<n>.
enable_d[8] 2.7.6 ValueState protocol Slave Compared with masked PVBus master id to select distributor interface: (master_id & enable_d<n>) == match_d<n>.
legacy_nfiq[8] 2.7.2 Signal protocol Slave Legacy FIQ interrupt for processor Interface <n>.
legacy_nirq[8] 2.7.2 Signal protocol Slave Input interrupt signals.
match_c[8] 2.7.6 ValueState protocol Slave Mask on the PVBus master id to select processor interface: (master_id & enable_c<n>) == match_c<n>.
match_d[8] 2.7.6 ValueState protocol Slave Mask on the PVBus master id to select distributor interface: (master_id & enable_d<n>) == match_d<n>.
nfiq[8] 2.7.2 Signal protocol Master Send out FIQ signal to processor <n>.
nirq[8] 2.7.2 Signal protocol Master Send out IRQ signal to processor <n>.
ppi_c0[16] 2.7.2 Signal protocol Slave Private peripheral interrupt for processor 0 (num_cpus> = 1).
ppi_c1[16] 2.7.2 Signal protocol Slave Private peripheral interrupt for processor 1 (num_cpus> = 2).
ppi_c2[16] 2.7.2 Signal protocol Slave Private peripheral interrupt for processor 2 (num_cpus> = 3).
ppi_c3[16] 2.7.2 Signal protocol Slave Private peripheral interrupt for processor 3 (num_cpus> = 4).
ppi_c4[16] 2.7.2 Signal protocol Slave Private peripheral interrupt for processor 4 (num_cpus> = 5).
ppi_c5[16] 2.7.2 Signal protocol Slave Private peripheral interrupt for processor 5 (num_cpus> = 6).
ppi_c6[16] 2.7.2 Signal protocol Slave Private peripheral interrupt for processor 6 (num_cpus> = 7).
ppi_c7[16] 2.7.2 Signal protocol Slave Private peripheral interrupt for processor 7 (num_cpus> = 8).
pvbus_cpu PVBus Slave Slave port for connection to processor interface.
pvbus_distributor PVBus Slave Slave port for connection to distributor interface.
reset_in 2.7.2 Signal protocol Slave Reset signal.
spi[988] 2.7.2 Signal protocol Slave Shared peripheral interrupt inputs.

Table 3-396 Parameters for PL390_GIC

Name Type Default value Description
ARCHITECTURE_VERSION int 0x1 set architecture version in periph_id register
AXI_IF bool 0x1 set interface type in peripheral identification register 8
C_ID_WIDTH int 0x20 width of the cpu interface master id
D_ID_WIDTH int 0x20 width of the distributor interface master id
ENABLE_LEGACY_FIQ bool 0x1 provide legacy fiq interrupt inputs
ENABLE_LEGACY_IRQ bool 0x1 provide legacy irq interrupt inputs
ENABLE_PPI_EDGE bool 0x0 ppi edge sensitive
ENABLE_TRUSTZONE bool 0x1 support trustzone
INIT_ENABLE_C0 int 0xffffffff initial value of register ENABLE_C0
INIT_ENABLE_C1 int 0xffffffff initial value of register ENABLE_C1
INIT_ENABLE_C2 int 0xffffffff initial value of register ENABLE_C2
INIT_ENABLE_C3 int 0xffffffff initial value of register ENABLE_C3
INIT_ENABLE_C4 int 0xffffffff initial value of register ENABLE_C4
INIT_ENABLE_C5 int 0xffffffff initial value of register ENABLE_C5
INIT_ENABLE_C6 int 0xffffffff initial value of register ENABLE_C6
INIT_ENABLE_C7 int 0xffffffff initial value of register ENABLE_C7
INIT_ENABLE_D0 int 0xffffffff initial value of register ENABLE_D0
INIT_ENABLE_D1 int 0xffffffff initial value of register ENABLE_D1
INIT_ENABLE_D2 int 0xffffffff initial value of register ENABLE_D2
INIT_ENABLE_D3 int 0xffffffff initial value of register ENABLE_D3
INIT_ENABLE_D4 int 0xffffffff initial value of register ENABLE_D4
INIT_ENABLE_D5 int 0xffffffff initial value of register ENABLE_D5
INIT_ENABLE_D6 int 0xffffffff initial value of register ENABLE_D6
INIT_ENABLE_D7 int 0xffffffff initial value of register ENABLE_D7
INIT_MATCH_C0 int 0x0 initial value of register MATCH_C0
INIT_MATCH_C1 int 0x1 initial value of register MATCH_C1
INIT_MATCH_C2 int 0x2 initial value of register MATCH_C2
INIT_MATCH_C3 int 0x3 initial value of register MATCH_C3
INIT_MATCH_C4 int 0x4 initial value of register MATCH_C4
INIT_MATCH_C5 int 0x5 initial value of register MATCH_C5
INIT_MATCH_C6 int 0x6 initial value of register MATCH_C6
INIT_MATCH_C7 int 0x7 initial value of register MATCH_C7
INIT_MATCH_D0 int 0x0 initial value of register MATCH_D0
INIT_MATCH_D1 int 0x1 initial value of register MATCH_D1
INIT_MATCH_D2 int 0x2 initial value of register MATCH_D2
INIT_MATCH_D3 int 0x3 initial value of register MATCH_D3
INIT_MATCH_D4 int 0x4 initial value of register MATCH_D4
INIT_MATCH_D5 int 0x5 initial value of register MATCH_D5
INIT_MATCH_D6 int 0x6 initial value of register MATCH_D6
INIT_MATCH_D7 int 0x7 initial value of register MATCH_D7
NUM_CPU int 0x8 number of cpu interfaces
NUM_LSPI int 0x1f number of lockable shared peripheral interrupts
NUM_PPI int 0x10 number of peripheral interrupts
NUM_PRIORITY_LEVELS int 0x100 number of priority levels
NUM_SGI int 0x10 number of software generated interrupts
NUM_SPI int 0x3dc number of shared peripheral interrupts
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