3.4.1 ARMAEMv8AMPCT

ARM AEM v8-A(MP) CPU component - number of core configurable at runtime. This model is written in C++.

The number of cores is configured using the NUM_CORES parameter. The per-core parameters are preceded by cpun, where n identifies the core (0-7).

AEMv8A core personalities

The AEM core personalities feature allows you to configure AEM instances in a platform to use the IMPLEMENTATION DEFINED registers and UNPREDICTABLE behavior for a specific implementation of your choice at model startup.

Configuring an AEM with a core personality requires a license for both the AEM and the selected implementation.

Set the personality using the environment variable FASTSIM_AEMV8_PROFILE, or the parameter impdef_regs_and_unpred_from_implementation.

The parameter allows you to configure different instances in the same platform with different personalities, including subclusters in a heterogeneous AEM. The environment variable takes precedence over the parameter and affects all instances of the AEM in the platform. Otherwise the two options function identically.

To see the available values for the environment variable or parameter, set either of them to the special value list. The model prints the list of available values and exits. An example value is ARM_Cortex-A57. Then set the parameter or environment variable to the required value.

Configuring a core personality only affects IMPLEMENTATION DEFINED registers and UNPREDICTABLE behavior. In other respects, the cluster or subcluster still behaves like the AEM. For example, all parameters default to the AEM default values. Therefore, parameters have to be manually configured to valid values for the configured personality, as many of the defaults are incompatible with any given implementation.

To assist with this configuration, the AEM prints warnings for any parameter with an invalid value for the configured personality. The warning lists the parameter name and the valid value or range of values it can be set to for the selected personality.

Running the model with invalid parameter configurations for the selected personality can lead to unexpected behavior.

Table 3-69 Ports

Name Protocol Type Description
CNTHPIRQ[8] 2.7.2 Signal protocol Master Timer signals to SOC.
CNTHPSIRQ[8] 2.7.2 Signal protocol Master Timer signals to SOC.
CNTHVIRQ[8] 2.7.2 Signal protocol Master Timer signals to SOC.
CNTHVSIRQ[8] 2.7.2 Signal protocol Master Timer signals to SOC.
CNTPNSIRQ[8] 2.7.2 Signal protocol Master Timer signals to SOC.
CNTPSIRQ[8] 2.7.2 Signal protocol Master Timer signals to SOC.
CNTVIRQ[8] 2.7.2 Signal protocol Master Timer signals to SOC.
CRITICALIRQ[8] 2.7.2 Signal protocol Master RAS Critical Error Interrupt.
ERRORIRQ[8] 2.7.2 Signal protocol Master RAS Error Recovery Interrupt.
FAULTIRQ[8] 2.7.2 Signal protocol Master RAS Fault Handling Interrupt
acp_s PVBus Slave AXI ACP slave port.
broadcastcachemaint 2.7.2 Signal protocol Slave ACE defined pins.
broadcastinner 2.7.2 Signal protocol Slave ACE defined pins.
broadcastouter 2.7.2 Signal protocol Slave ACE defined pins.
cfgend[8] 2.7.2 Signal protocol Slave This signal if for EE bit initialisation.
cfgsdisable 2.7.2 Signal protocol Slave This signal disables write access to some secure Interrupt Controller registers.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
clrexmonack 2.7.2 Signal protocol Master Acknowledge handshake signal for the clrexmonreq signal
clrexmonreq 2.7.2 Signal protocol Slave Signals the clearing of an external global exclusive monitor
clusterid 2.7.4 Value protocol Slave The port reads the value in CPU ID register field, bits[11:8] of the MPIDR.
cntvalueb 2.6.1 CounterInterface protocol Slave Interface to SoC level counter module.
commirq[8] 2.7.2 Signal protocol Master Interrupt signal from debug communications channel.
config64[8] 2.7.2 Signal protocol Slave Register width after reset.
cp15sdisable[8] 2.7.2 Signal protocol Slave This signal disables write access to some system control processor registers.
cpuporeset[8] 2.7.2 Signal protocol Slave CPU power on reset. Initializes all the processor logic, including debug logic.
cryptodisable[8] 2.7.2 Signal protocol Slave Disable cryptography extensions after reset.
cti[8] 2.6.4 v8EmbeddedCrossTrigger_controlprotocol protocol Master Cross trigger matrix port.
cti0extin[4] 2.7.2 Signal protocol Slave CTI trace inputs for core 0.
cti0extout[4] 2.7.2 Signal protocol Master CTI trace outputs for core 0.
cti1extin[4] 2.7.2 Signal protocol Slave CTI trace inputs for core 1.
cti1extout[4] 2.7.2 Signal protocol Master CTI trace outputs for core 1.
cti2extin[4] 2.7.2 Signal protocol Slave CTI trace inputs for core 2.
cti2extout[4] 2.7.2 Signal protocol Master CTI trace outputs for core 2.
cti3extin[4] 2.7.2 Signal protocol Slave CTI trace inputs for core 3.
cti3extout[4] 2.7.2 Signal protocol Master CTI trace outputs for core 3.
cti4extin[4] 2.7.2 Signal protocol Slave CTI trace inputs for core 4.
cti4extout[4] 2.7.2 Signal protocol Master CTI trace outputs for core 4.
cti5extin[4] 2.7.2 Signal protocol Slave CTI trace inputs for core 5.
cti5extout[4] 2.7.2 Signal protocol Master CTI trace outputs for core 5.
cti6extin[4] 2.7.2 Signal protocol Slave CTI trace inputs for core 6.
cti6extout[4] 2.7.2 Signal protocol Master CTI trace outputs for core 6.
cti7extin[4] 2.7.2 Signal protocol Slave CTI trace inputs for core 7.
cti7extout[4] 2.7.2 Signal protocol Master CTI trace outputs for core 7.
ctidbgirq[8] 2.7.2 Signal protocol Master Cross Trigger Interface (CTI) interrupt trigger output.
dbgen[8] 2.7.2 Signal protocol Slave External debug interface.
dbgnopwrdwn[8] 2.7.2 Signal protocol Master Debug no power down request.
dbgpwrdwnack[8] 2.7.2 Signal protocol Master Debug power down acknowledge.
dbgpwrdwnreq[8] 2.7.2 Signal protocol Slave Debug power down request.
dbgpwrupreq[8] 2.7.2 Signal protocol Master Debug power up request.
dev_debug_s PVBus Slave External debug interface.
etm[8] PVBus Master Embedded trace macrocell port.
event 2.7.2 Signal protocol Peer This peer port of event input (and output) is for wakeup from WFE.
external_trace_reset[8] 2.7.2 Signal protocol Slave ETMv4 External Trace Reset signal.
fiq[8] 2.7.2 Signal protocol Slave This signal drives the CPUs fast-interrupt handling.
gicv3_redistributor_s[8] 2.6.2 GICv3Comms protocol Slave GICv3 cpu interface ports.
irq[8] 2.7.2 Signal protocol Slave This signal drives the CPUs interrupt handling.
irqs[224] 2.7.2 Signal protocol Slave These signals drive the CPU's interrupt controller interrupt lines.
l2reset 2.7.2 Signal protocol Slave This signal resets timer and interrupt controller.
memorymapped_debug_s PVBus Slave External debug interface.
niden[8] 2.7.2 Signal protocol Slave External debug interface.
periphbase 2.7.5 Value_64 protocol Slave This port sets the base address of private peripheral region.
pmbirq[8] 2.7.2 Signal protocol Master Interrupt signal from the statistical profiling unit.
pmuirq[8] 2.7.2 Signal protocol Master Interrupt signal from performance monitoring unit.
presetdbg[8] 2.7.2 Signal protocol Slave Initialize the shared debug APB, Cross Trigger Interface (CTI), and Cross Trigger Matrix (CTM) logic.
pvbus_m0 PVBus Master The core will generate bus requests on this port.
rei[8] 2.7.2 Signal protocol Slave Individual processor RAM Error Interrupt signal input.
reset[8] 2.7.2 Signal protocol Slave Raising this signal will put the core into reset mode.
romaddr 2.7.5 Value_64 protocol Slave Debug ROM base address.
romaddrv 2.7.2 Signal protocol Slave Debug ROM base address valid.
rvbar[8] 2.7.5 Value_64 protocol Slave Reset vector base address.
sei[8] 2.7.2 Signal protocol Slave Per core System Error physical pins.
smpnamp[8] 2.7.2 Signal protocol Master This signals AMP or SMP mode for each core.
spiden[8] 2.7.2 Signal protocol Slave External debug interface.
spniden[8] 2.7.2 Signal protocol Slave External debug interface.
standbywfe[8] 2.7.2 Signal protocol Master This signal indicates if a core is in WFE state.
standbywfi[8] 2.7.2 Signal protocol Master This signal indicates if a core is in WFI state.
standbywfil2 2.7.2 Signal protocol Master This signal indicated all cores and L2 are in a power down state
teinit[8] 2.7.2 Signal protocol Slave This signal provides default exception handling state.
ticks[8] 2.6.3 InstructionCount protocol Master This port should be connected to one of the two ticks ports on a 'visualisation' component, in order to display a running instruction count.
trace_unit_reset[8] 2.7.2 Signal protocol Slave ETMv4 Trace Unit Reset signal.
vcpumntirq[8] 2.7.2 Signal protocol Master Interrupt signal for virtual CPU maintenance IRQ.
vfiq[8] 2.7.2 Signal protocol Slave Virtual FIQ input. Note that the irq/fiq pins are wired directly to the core if there is no internal VGIC. If there is an internal VGIC then these are ignored.
vinithi[8] 2.7.2 Signal protocol Slave This signal controls of the location of the exception vectors at reset.
virq[8] 2.7.2 Signal protocol Slave Virtual IRQ input. Note that the irq/fiq pins are wired directly to the core if there is no internal VGIC. If there is an internal VGIC then these are ignored.
virtio_s PVBus Slave The virtio coherent port, hooks directly into the L2 system and becomes coherent (assuming attributes are set correctly).
vsei[8] 2.7.2 Signal protocol Slave Processor Virtual System Error Interrupt request.

Table 3-70 Parameters for Cluster_ARMAEMv8-A_MP

Name Type Default value Description
ADFSR-AIFSR-implemented bool 0x0 ADFSR and AIFSR are implemented
AIDR int 0x0 Value of AIDR_EL1 register.
BPIMVA_causes_translation_lookup bool 0x0 Do a translation when BPIMVA instruction is executed (which may cause a translation fault).
CCSIDR-L1D_override int 0x0 If nonzero, override the value presented in CCSIDR for L1D (this is cosmetic and does not affect cache behaviour).
CCSIDR-L1I_override int 0x0 If nonzero, override the value presented in CCSIDR for L1I (this is cosmetic and does not affect cache behaviour).
CCSIDR-L2_override int 0x0 If nonzero, override the value presented in CCSIDR for L2 (this is cosmetic and does not affect cache behaviour).
CCSIDR-L3_override int 0x0 If nonzero, allow L3 selection in CSSELR and present this value in CCSIDR (this is cosmetic and does not affect cache behaviour).
CLUSTER_ID int 0x0 Processor cluster ID value
CTIPIDR int 0x0 If non-zero, override the CTI Peripheral Identification Register
CTR-L1Ip-override int 0x0 If non-zero, override the L1Ip bits in CTR/CTR_EL0 system register. This does not change the behaviour of the cache, only what is present in the CTR register.
DBGBCR_BT_applies_RES0_before_valid_check bool 0x1 If true, RES0 behaviour is applied to DBGBCR(_EL1).BT before checking for reserved values for this field.
DBGPIDR int 0x0 If non-zero, override the Debug Peripheral Identification Register
ERXMISC0_mask int 0x0 Write Mask for ERXMISC0 RAS Register
MIDR int 0x410fd0f0 Value of MIDR_EL1 register.
NUM_CORES int 0x1 Number of cores per cluster
PA_SIZE int 0x28 Physical address range supported. For ARMv8.0 and ARMv8.1 this is limited to 48 bits.
PERIPHBASE int 0x13080000 Base address of peripheral memory space
PMUPIDR int 0x0 If non-zero, override the PMU Peripheral Identification Register
abort_execution_from_device_memory bool 0x0 Execution from device memory generates a prefetch abort.
advsimd_overread bool 0x0 AdvSIMD element load operations access all bytes of a 16-byte aligned window, even in Device memory
align_pc_on_debug_exit_to_aarch32 bool 0x0 Exit to AARCH32 state from debug state forces pc bit0 to 0
align_pc_on_illegal_exception_return_to_aarch32 bool 0x1 Align PC when performing an illegal exception return from AArch64 to AArch32.
amu_has_external_interface int 0x0 Implement external memory-mapped access to system register of activity monitor unit from ARMv8.4. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
apsr_read_restrict bool 0x0 At EL0, unknown bits of APSR are RAZ.
auxilliary_feature_register0 int 0x0 Value of AFR0 ID register.
branch-predictor-clear-policy int 0x2 Set branch prediction policy as defined for MMFR1[31:28]. This does not change the behaviour of the branch predictor, only what is reported in MMFR1.BPred.
branch-predictor-supported-ops int 0x1 Set branch prediction policy as defined for MMFR3[11:8]. This does not change the behaviour of the branch predictor, only what is reported in MMFR3.BPMaint.
cache-log2linelen int 0x6 Log2 of the cache line length in bytes.
cache_maintenance_hits_watchpoints bool 0x0 DCIMVA operations executed in AArch32 modes hit watchpoints.
changing_block_size_without_bbm_support int 0x0 Level of support for changing block size without break-before-make.
check_memory_attributes bool 0x1 Detect and report TLB use of conflicting memory attributes for views of the same physical address
clear_reg_top_eret int 0x1 Behaviour of the upper 32-bits of the Xn registers when changing between AArch32 state and AArch64 state. 0, upper 32-bits preserved for all registers. 1, upper 32-bits set to 0 for all accessible registers. 2, upper 32-bits set to 0 for a random selection of accessible registers. 3, upper-32-bits set to 0 for registers touched in AArch32
cpacr_trcdis_behaviour int 0x2 Behaviour of CPACR.TRCDIS/NSACR.NSTRCDIS when there is no CP14 ETM interface. 0, RAZ/WI. 2, implemented.
cpi_div int 0x1 Divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 Multiplier for calculating CPI (Cycles Per Instruction)
dbgitr_buffer_size int 0x0 Number of instructions which can be bufferred before EDSCR.ITE is cleared
dcache-hit_latency int 0x0 L1 D-Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when dcache-state_modelled=true.
dcache-maintenance_latency int 0x0 L1 D-Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when dcache-state_modelled=true.
dcache-miss_latency int 0x0 L1 D-Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when dcache-state_modelled=true.
dcache-prefetch_enabled bool 0x0 Enable simulation of data cache prefetching. This is only used when dcache-state_modelled=true
dcache-read_access_latency int 0x0 L1 D-Cache timing annotation latency for read accesses given in ticks per access (of size dcache-read_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if dcache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, this is only used when dcache-state_modelled=true.
dcache-read_bus_width_in_bytes int 0x8 L1 D-Cache read bus width in bytes used to calculate per-access timing annotations
dcache-read_latency int 0x0 L1 D-Cache timing annotation latency for read accesses given in ticks per byte accessed.dcache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when dcache-state_modelled=true.
dcache-size int 0x8000 L1 D-Cache size in bytes.
dcache-snoop_data_transfer_latency int 0x0 L1 D-Cache timing annotation latency for received snoop accesses that perform a data transfer given in ticks per byte accessed. This is only used when dcache-state_modelled=true.
dcache-state_modelled bool 0x0 Set whether D-cache has stateful implementation
dcache-ways int 0x2 L1 D-Cache number of ways (sets are implicit from size).
dcache-write_access_latency int 0x0 L1 D-Cache timing annotation latency for write accesses given in ticks per access (of size dcache-write_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if dcache-write_latency is set. This is only used when dcache-state_modelled=true.
dcache-write_bus_width_in_bytes int 0x8 L1 D-Cache write bus width in bytes used to calculate per-access timing annotations
dcache-write_latency int 0x0 L1 D-Cache timing annotation latency for write accesses given in ticks per byte accessed. dcache-write_access_latency must be set to 0 for per-byte latencies to be applied. This is only used when dcache-state_modelled=true.
dcimva_requires_s2_write_permissions bool 0x0 Data-cache invalidate by MVA operations require stage 2 write permission (virtualised AArch32 guest).
debug_rom_is_class_9 bool 0x0 If true, present a debug ROM table as a class 9 device. Otherwise, use a class 1 ROM table.
debug_rom_is_flat bool 0x0 If true, present a debug ROM table recommended by ARMv8 Debug Architecture. Otherwise, use nested ROM tables.
delay_serror int 0x0 Add a propagation delay of serror signal into the core
delayed_dbgreg_between_secure_views int 0x1 If delayed_dbgreg is enabled, whether the secure and nonsecure external views require explicit synchronization. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
dic-spi_count int 0x40 Number of shared peripheral interrupts implemented
disable_sve_plugin bool 0x0 If true, SVE will not be implemented in this processor even if the plugin is loaded
edpfr_ras_unknown_bits_read_as_0 bool 0x0 If true then UNKNOWN bits in RAS field in EDPFR are read as 0
el0_can_access_imp_def_functionality bool 0x0 If not made UNDEF by imp_def_functionality_behaviour, EL0 can access IMPLEMENTATION DEFINED registers and system instructions.
el0_el1_only_non_secure bool 0x0 Secure/non-secure state if EL2 and EL3 are not implemented. 0, secure. 1, non-secure.
enable_tlb_contig_check bool 0x0 Perform extra pagetable walks to check translation table entries that have the contiguous hint bit set.
error_record_feature_register string "" RAS feature register values. An array of JSON objects. The JSON schema for the array is: [{"ED":0x0,"UI":0x0,"FI":0x0,"UE":0x0,"CFI":0x0,"CEC":0x0,"RP":0x0,"DUI":0x0,"CEO":0x0,"CI":0x0,"TS":0x0,"INJ":0x0,"Visibility":"Core"},other_feature_register_values]. Where ED,UI,FI, and UE have valid values betwn 0x0 - 0x3. CFI and DUI have valid values 0x0, 0x2 and 0x3. CEC has valid values 0x0,0x2 or 0x4. RP has valid value 0x0 or 0x1. CEO has valid values of 0x0 and 0x1. CI and TS has valid values of 0x0, 0x1 and 0x2. INJ has valid values 0x0 or 0x1. Visibility has valid values "Core" or "Cluster"
error_record_feature_register_json_file string "" File path to the RAS feature register values as JSON. The file uses the same format as the error_record_feature_register parameter value
exception_catch_type int 0x0 Type of exception catch (ARMv8.0 - ARMv8.1 only). 0, exception trapping. 1, non-exception trapping, higher priority than step. 2, non-exception-trapping, lower priority than step.
exclusive_monitor_clear_on_atomic_from_same_master bool 0x1 Exclusive monitors in the cluster will be cleared by a atomic by the same master to the monitored address.
exclusive_monitor_clear_on_store_from_same_master bool 0x1 Exclusive monitors in the cluster will be cleared by a store by the same master to the monitored address.
exclusive_monitor_clear_on_strex_address_mismatch bool 0x1 Exclusive monitors in the cluster will be cleared when a strex fails because the address does not match.
exclusive_monitor_clear_on_strex_success bool 0x1 Exclusive monitors in the cluster will be cleared when a strex succeeds.
exercise_stxr_fail bool 0x0 Reject a pseudo-random majority of exclusive store instructions
ext_abort_device_GRE_prefetch_ras_index int -0x1 External Aborts are reported in RAS record index specified in this param. Values: -1 = Same as ext_abort_prefetch_ras_index, Valid indices in range [0, number_of_error_records).
ext_abort_device_GRE_prefetch_ras_type int -0x1 External Aborts are reported as RAS error type specified in this param. Values: -1 = Same as ext_abort_prefetch_ras_type, 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_device_GRE_read_is_critical bool 0x0 Critical reporting of device-GRE read external aborts.
ext_abort_device_GRE_read_is_sync int 0x2 Synchronous reporting of device-GRE read external aborts. 0, asynchronous. 1, synchronous. 2, same as ext_abort_device_read_is_sync.
ext_abort_device_GRE_read_ras_index int -0x1 External Aborts are reported in RAS record index specified in this param. Values: -1 = Same as ext_abort_device_read_ras_index, Valid indices in range [0, number_of_error_records).
ext_abort_device_GRE_read_ras_type int -0x1 External Aborts are reported as RAS error type specified in this param. Values: -1 = Same as ext_abort_device_read_ras_type, 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_device_GRE_write_is_critical bool 0x0 Critical reporting of device-GRE write external aborts
ext_abort_device_GRE_write_is_sync int 0x2 Synchronous reporting of device-GRE write external aborts. 0, asynchronous. 1, synchronous. 2, same as ext_abort_device_write_is_sync.
ext_abort_device_GRE_write_ras_index int -0x1 External Aborts are reported in RAS record index specified in this param. Values: -1 = Same as ext_abort_device_write_ras_index, Valid indices in range [0, number_of_error_records).
ext_abort_device_GRE_write_ras_type int -0x1 External Aborts are reported as RAS error type specified in this param. Values: -1 = Same as ext_abort_device_write_ras_type, 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_device_nGRE_prefetch_ras_index int -0x1 External Aborts are reported in RAS record index specified in this param. Values: -1 = Same as ext_abort_prefetch_ras_index, Valid indices in range [0, number_of_error_records).
ext_abort_device_nGRE_prefetch_ras_type int -0x1 External Aborts are reported as RAS error type specified in this param. Values: -1 = Same as ext_abort_prefetch_ras_type, 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_device_nGRE_read_is_critical bool 0x0 Critical reporting of device-nGRE read external aborts.
ext_abort_device_nGRE_read_is_sync int 0x2 Synchronous reporting of device-nGRE read external aborts. 0, asynchronous. 1, synchronous. 2, same as ext_abort_device_read_is_sync.
ext_abort_device_nGRE_read_ras_index int -0x1 External Aborts are reported in RAS record index specified in this param. Values: -1 = Same as ext_abort_device_read_ras_index, Valid indices in range [0, number_of_error_records).
ext_abort_device_nGRE_read_ras_type int -0x1 External Aborts are reported as RAS error type specified in this param. Values: -1 = Same as ext_abort_device_read_ras_type, 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_device_nGRE_write_is_critical bool 0x0 Critical reporting of device-nGRE write external aborts
ext_abort_device_nGRE_write_is_sync int 0x2 Synchronous reporting of device-nGRE write external aborts. 0, asynchronous. 1, synchronous. 2, same as ext_abort_device_write_is_sync.
ext_abort_device_nGRE_write_ras_index int -0x1 External Aborts are reported in RAS record index specified in this param. Values: -1 = Same as ext_abort_device_write_ras_index, Valid indices in range [0, number_of_error_records).
ext_abort_device_nGRE_write_ras_type int -0x1 External Aborts are reported as RAS error type specified in this param. Values: -1 = Same as ext_abort_device_write_ras_type, 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_device_prefetch_ras_index int -0x1 External Aborts are reported in RAS record index specified in this param. Values: -1 = Same as ext_abort_prefetch_ras_index, Valid indices in range [0, number_of_error_records).
ext_abort_device_prefetch_ras_type int -0x1 External Aborts are reported as RAS error type specified in this param. Values: -1 = Same as ext_abort_prefetch_ras_type, 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_device_read_is_critical bool 0x0 Critical reporting of device-nGnRE read external aborts
ext_abort_device_read_is_sync bool 0x1 Synchronous reporting of device-nGnRE read external aborts
ext_abort_device_read_ras_index int 0x0 External Aborts are reported in RAS record index specified in this param. Values: Valid indices in range [0, number_of_error_records).
ext_abort_device_read_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_device_write_is_critical bool 0x0 Critical reporting of device-nGnRE write external aborts
ext_abort_device_write_is_sync bool 0x0 Synchronous reporting of device-nGnRE write external aborts
ext_abort_device_write_ras_index int 0x0 External Aborts are reported in RAS record index specified in this param. Values: Valid indices in range [0, number_of_error_records).
ext_abort_device_write_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_fill_data int -0x202020303020203 Returned data, if external aborts are asynchronous
ext_abort_normal_cacheable_read_is_critical bool 0x0 Critical reporting of normal write-back cacheable-read external aborts
ext_abort_normal_cacheable_read_is_sync bool 0x1 Synchronous reporting of normal write-back cacheable-read external aborts
ext_abort_normal_cacheable_read_ras_index int 0x0 External Aborts are reported in RAS record index specified in this param. Values: Valid indices in range [0, number_of_error_records).
ext_abort_normal_cacheable_read_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_normal_cacheable_write_is_critical bool 0x0 Critical reporting of normal write-back cacheable write external aborts
ext_abort_normal_cacheable_write_is_sync bool 0x0 Synchronous reporting of normal write-back cacheable write external aborts
ext_abort_normal_cacheable_write_ras_index int 0x0 External Aborts are reported in RAS record index specified in this param. Values: Valid indices in range [0, number_of_error_records).
ext_abort_normal_cacheable_write_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_normal_noncacheable_prefetch_ras_index int -0x1 External Aborts are reported in RAS record index specified in this param. Values: -1 = Same as ext_abort_prefetch_ras_index, Valid indices in range [0, number_of_error_records).
ext_abort_normal_noncacheable_prefetch_ras_type int -0x1 External Aborts are reported as RAS error type specified in this param. Values: -1 = Same as ext_abort_prefetch_ras_type, 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_normal_noncacheable_read_is_critical bool 0x0 Critical reporting of normal noncacheable-read external aborts
ext_abort_normal_noncacheable_read_is_sync bool 0x1 Synchronous reporting of normal noncacheable-read external aborts
ext_abort_normal_noncacheable_read_ras_index int 0x0 External Aborts are reported in RAS record index specified in this param. Values: Valid indices in range [0, number_of_error_records).
ext_abort_normal_noncacheable_read_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_normal_noncacheable_write_is_critical bool 0x0 Critical reporting of normal noncacheable write external aborts
ext_abort_normal_noncacheable_write_is_sync bool 0x0 Synchronous reporting of normal noncacheable write external aborts
ext_abort_normal_noncacheable_write_ras_index int 0x0 External Aborts are reported in RAS record index specified in this param. Values: Valid indices in range [0, number_of_error_records).
ext_abort_normal_noncacheable_write_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_normal_wt_cacheable_prefetch_ras_index int -0x1 External Aborts are reported in RAS record index specified in this param. Values: -1 = Same as ext_abort_prefetch_ras_index, Valid indices in range [0, number_of_error_records).
ext_abort_normal_wt_cacheable_prefetch_ras_type int -0x1 External Aborts are reported as RAS error type specified in this param. Values: -1 = Same as ext_abort_prefetch_ras_type, 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_normal_wt_cacheable_read_is_critical bool 0x0 Critical reporting of normal write-through cacheable-read external aborts
ext_abort_normal_wt_cacheable_read_is_sync int 0x2 Synchronous reporting of normal write-through read external aborts. 0, asynchronous. 1, synchronous. 2, same as ext_abort_normal_cacheable_read_is_sync.
ext_abort_normal_wt_cacheable_read_ras_index int -0x1 External Aborts are reported in RAS record index specified in this param. Values: -1 = Same as ext_abort_normal_cacheable_read_ras_index, Valid indices in range [0, number_of_error_records).
ext_abort_normal_wt_cacheable_read_ras_type int -0x1 External Aborts are reported as RAS error type specified in this param. Values: -1 = Same as ext_abort_normal_cacheable_read_ras_type, 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_normal_wt_cacheable_write_is_critical bool 0x0 Critical reporting of normal write-through write external aborts
ext_abort_normal_wt_cacheable_write_is_sync int 0x2 Synchronous reporting of normal write-through write external aborts. 0, asynchronous. 1, synchronous. 2, same as ext_abort_normal_cacheable_write_is_sync.
ext_abort_normal_wt_cacheable_write_ras_index int -0x1 External Aborts are reported in RAS record index specified in this param. Values: -1 = Same as ext_abort_normal_cacheable_write_ras_index, Valid indices in range [0, number_of_error_records).
ext_abort_normal_wt_cacheable_write_ras_type int -0x1 External Aborts are reported as RAS error type specified in this param. Values: -1 = Same as ext_abort_normal_cacheable_write_ras_type, 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_prefetch_device_GRE_read_is_critical bool 0x0 Critical reporting of external aborts generated by device-GRE instruction fetches
ext_abort_prefetch_device_GRE_read_is_sync int 0x2 Behaviour of external aborts generated by device-GRE instruction fetches. 0, asynchronous abort. 1, synchronous abort. 2, same as ext_abort_prefetch_is_sync.
ext_abort_prefetch_device_nGRE_read_is_critical bool 0x0 Critical reporting of external aborts generated by device-nGRE instruction fetches
ext_abort_prefetch_device_nGRE_read_is_sync int 0x2 Behaviour of external aborts generated by device-nGRE instruction fetches. 0, asynchronous abort. 1, synchronous abort. 2, same as ext_abort_prefetch_is_sync.
ext_abort_prefetch_device_read_is_critical bool 0x0 Critical reporting of external aborts generated by device-nGnRE instruction fetches
ext_abort_prefetch_device_read_is_sync int 0x2 Behaviour of external aborts generated by device-nGnRE instruction fetches. 0, asynchronous abort. 1, synchronous abort. 2, same as ext_abort_prefetch_is_sync.
ext_abort_prefetch_is_critical bool 0x0 Critical reporting of external aborts generated by normal writeback cacheable instruction fetches
ext_abort_prefetch_is_sync bool 0x1 Behaviour of external aborts generated by normal writeback cacheable instruction fetches. 0, asynchronous abort. 1, synchronous abort.
ext_abort_prefetch_noncacheable_read_is_critical bool 0x0 Critical reporting of external aborts generated by normal noncacheable instruction fetches
ext_abort_prefetch_noncacheable_read_is_sync int 0x2 Behaviour of external aborts generated by normal noncacheable instruction fetches. 0, asynchronous abort. 1, synchronous abort. 2, same as ext_abort_prefetch_is_sync.
ext_abort_prefetch_ras_index int 0x0 External Aborts are reported in RAS record index specified in this param. Values: Valid indices in range [0, number_of_error_records).
ext_abort_prefetch_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_prefetch_so_read_is_critical bool 0x0 Critical reporting of external aborts generated by device-nGnRnE instruction fetches
ext_abort_prefetch_so_read_is_sync int 0x2 Behaviour of external aborts generated by device=nGnRnE instruction fetches. 0, asynchronous abort. 1, synchronous abort. 2, same as ext_abort_prefetch_is_sync.
ext_abort_prefetch_wt_cacheable_read_is_critical bool 0x0 Critical reporting of external aborts generated by normal writethrough cacheable instruction fetches
ext_abort_prefetch_wt_cacheable_read_is_sync int 0x2 Behaviour of external aborts generated by normal writethrough cacheable instruction fetches. 0, asynchronous abort. 1, synchronous abort. 2, same as ext_abort_prefetch_is_sync.
ext_abort_so_prefetch_ras_index int -0x1 External Aborts are reported in RAS record index specified in this param. Values: -1 = Same as ext_abort_prefetch_ras_index, Valid indices in range [0, number_of_error_records).
ext_abort_so_prefetch_ras_type int -0x1 External Aborts are reported as RAS error type specified in this param. Values: -1 = Same as ext_abort_prefetch_ras_type, 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_so_read_is_critical bool 0x0 Critical reporting of device-nGnRnE read external aborts
ext_abort_so_read_is_sync bool 0x1 Synchronous reporting of device-nGnRnE read external aborts
ext_abort_so_read_ras_index int 0x0 External Aborts are reported in RAS record index specified in this param. Values: Valid indices in range [0, number_of_error_records).
ext_abort_so_read_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_so_write_is_critical bool 0x0 Critical reporting of device-nGnRnE write external aborts
ext_abort_so_write_is_sync bool 0x1 Synchronous reporting of device-nGnRnE write external aborts
ext_abort_so_write_ras_index int 0x0 External Aborts are reported in RAS record index specified in this param. Values: Valid indices in range [0, number_of_error_records).
ext_abort_so_write_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_ttw_cacheable_read_is_critical bool 0x0 Critical reporting of TTW cacheable read external aborts
ext_abort_ttw_cacheable_read_is_sync bool 0x1 Synchronous reporting of TTW cacheable read external aborts
ext_abort_ttw_cacheable_read_ras_index int 0x0 External Aborts are reported in RAS record index specified in this param. Values: Valid indices in range [0, number_of_error_records).
ext_abort_ttw_cacheable_read_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_ttw_noncacheable_read_is_critical bool 0x0 Critical reporting of TTW noncacheable read external aborts
ext_abort_ttw_noncacheable_read_is_sync bool 0x1 Synchronous reporting of TTW noncacheable read external aborts
ext_abort_ttw_noncacheable_read_ras_index int 0x0 External Aborts are reported in RAS record index specified in this param. Values: Valid indices in range [0, number_of_error_records).
ext_abort_ttw_noncacheable_read_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_ttw_wt_cacheable_read_is_critical bool 0x0 Critical reporting of TTW write-through cacheable read external aborts
ext_abort_ttw_wt_cacheable_read_is_sync int 0x2 Synchronous reporting of TTW write-through cacheable read external aborts. 0, asynchronous. 1, synchronous. 2, same as ext_abort_ttw_cacheable_read_is_sync.
ext_abort_ttw_wt_cacheable_read_ras_index int -0x1 External Aborts are reported in RAS record index specified in this param. Values: -1 = Same as ext_abort_ttw_cacheable_read_ras_index, Valid indices in range [0, number_of_error_records).
ext_abort_ttw_wt_cacheable_read_ras_type int -0x1 External Aborts are reported as RAS error type specified in this param. Values: -1 = Same as ext_abort_ttw_cacheable_read_ras_type, 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
fault_on_nT_bit_set bool 0x1 Whether block translation table entries with the nT bit set should always fault. Only applies when changing_block_size_without_bbm_support_level is 1 or higher.
force_align_pc bool 0x0 UNPREDICTABLE branch to non-word-aligned address in ARM state is forced to be aligned
force_deterministic_irg_tag_generation bool 0x0 Force the random tag generated by the IRG instruction when GCR_EL1.RRND=1 to equal RGSR_EL1.SEED[3:0] rather than a non-deterministic value
fpcr_short_vector_raz bool 0x0 FPSCR and FPCR fields LEN and STRIDE are hardwired to 0
hardware_translation_table_update_implemented int 0x1 Implement hardware translation table updates from ARMv8.1. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.1 is enabled. - 2, feature is implemented.
has_16bit_asids bool 0x1 Enable 16-bit ASIDs.
has_16bit_vmids int 0x1 Implement support for 16-bit VMIDs from ARMv8.1. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.1 is enabled. - 2, feature is implemented.
has_16k_granule bool 0x0 Implement the 16k LPAE translation granule.
has_4k_granule bool 0x1 Implement the 4k LPAE translation granule.
has_64k_granule bool 0x1 Implement the 64k LPAE translation granule.
has_aarch32_dbgdidr_etc bool 0x1 DBGDIDR, DBGDRAR, DBGDSAR exist even if EL1 doesn't implement AArch32
has_aarch32_hpd bool 0x0 If true then hierarchical permission disable is supported in AArch32
has_aarch64 bool 0x1 All implemented exception levels can run in AArch64
has_actlr2 bool 0x0 If true ACLTR2 exists and ACTLR2(NS) is aliased to ACTLR_EL1[63:32]
has_amu int 0x0 Implement activity monitor functionality from ARMv8.4. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_arm_v8-1 bool 0x0 Implement the ARMv8.1 Extension.
has_arm_v8-2 bool 0x0 Implement the ARMv8.2 Extension.
has_arm_v8-3 bool 0x0 Implement the ARMv8.3 Extension.
has_arm_v8-4 bool 0x0 Implement the ARMv8.4 Extension. This feature is incomplete and under development.
has_arm_v8-5 bool 0x0 Implement the ARMv8.5 Extension. This feature is incomplete and under development.
has_at_with_pan int 0x1 Implement new AT instructions with PAN support. Possible values of this parameter are: - 1, feature is implemented if ARMv8.2 is enabled. - 2, feature is implemented.
has_axflag_xaflag_frint int 0x1 Implement flag manipulation instructions (AXFlag, XAFlag, FRINT[32|64][X|Z]) from ARMv8.5. Possible values of this parameter are: - 1, feature is implemented if ARMv8.5 is enabled. - 2, feature is implemented.
has_branch_target_exception int 0x0 Implement Branch target identification mechanism from ARMv8.5. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.5 is enabled. - 2, feature is implemented.
has_ccidx bool 0x0 Implement the ARMv8.3 CCSIDR Extension. Extending the ccsidr number of sets.
has_cfinv_rmif_setf int 0x1 Implement flag manipulation (CFINV, RMIF, SETF8, SETF16) instructions from ARMv8.4. Possible values of this parameter are: - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_coherent_icache bool 0x0 Whether icache invalidation to the point of unification is required for instruction to data coherence. true - Invalidate operations not required
has_common_not_private_translations int 0x1 Implement the TTBRn_ELx.CnP (Common not Private) controls from ARMv8.2. Possible values of this parameter are: - 1, feature is implemented if ARMv8.2 is enabled. - 2, feature is implemented.
has_complex_number int 0x1 Implement ARMv8.3 complex number support, Multiply Accumulate and Add instructions. Possible values of this parameter are: - 1, feature is implemented if ARMv8.3 is enabled. - 2, feature is implemented.
has_cvadp_support int 0x1 Implement instruction to support cache clean by deep persistence (DC CVADP) from ARMv8.5, can be selected for core implemented on any arch version starting ARMv8.2 Possible values of this parameter are: - 1, feature is implemented if ARMv8.5 is enabled. - 2, feature is implemented.
has_data_alignment_flag int 0x0 Implement non-optimal misalignment flag for PMU/SPE from ARMv8.5 Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.5 is enabled. - 2, feature is implemented.
has_debug_rom bool 0x1 If true, a debug ROM will be generated describing the cluster's debug components.
has_delayed_ctireg bool 0x0 Delay the functional effect of CTI register writes until ISB or implicit barrier.
has_delayed_dbgreg bool 0x0 Delay the functional effect of external debug register writes until ISB or implicit barrier.
has_delayed_sysreg bool 0x0 Delay the functional effect of system register writes until ISB or implicit barrier.
has_dot_product int 0x1 Implement the dot product (UDOT, SDOT) instructions from ARMv8.4. Possible values of this parameter are: - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_e0pd int 0x1 Implement ARMv8.5 feature to prevent unprivileged access to one half of the memory Possible values of this parameter are: - 1, feature is implemented if ARMv8.5 is enabled. - 2, feature is implemented.
has_edacr bool 0x1 Implement EDACR register
has_el2 bool 0x1 Implements EL2
has_el3 bool 0x1 Implements EL3
has_enhanced_pac bool 0x0 If pointer authentication is enabled then implement enhanced PAC.
has_exception_trapping_form_of_vector_catch bool 0x1 Implement the exception trapping form of vector catch debug event.
has_far_not_valid bool 0x0 Implements FnV bit in ESR_ELx and xFSR, FAR not valid for synchronous external aborts.
has_fp16 int 0x1 Implement the half-precision floating-point data processing instructions from ARMv8.2. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.2 is enabled. - 2, feature is implemented.
has_fp16_fmlal int 0x1 Implement the New Floating Point Multiplication Variant (FP16 FMLAL, FMLSL) instructions from ARMv8.4. Only supported if has_fp16=0x1. Possible values of this parameter are: - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_generic_authentication int 0x1 Implement ARMv8.3 generic authentication. Possible values of this parameter are: - 1, feature is implemented if ARMv8.3 is enabled. - 2, feature is implemented.
has_guest_translation_granule int 0x1 Implement mechanism for guest translation granule identification from ARMv8.5, ID values determined by stage1 granule configuration parameters Possible values of this parameter are: - 1, feature is implemented if ARMv8.5 is enabled. - 2, feature is implemented.
has_hardware_translation_table_update int 0x2 Type of hardware translation table supported (when enabled by hardware_translation_table_update_implemented). 0, not implemented. 1, access bit updates implemented. 2, access bit updates and dirty bit mechanism implemented.
has_id_reg_read int 0x1 Implement read access to the ID registers (ESR_ELx.EC=0x18) Possible values of this parameter are: - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_itd bool 0x1 Implement the optional IT disable feature.
has_jscvt int 0x1 Implement ARMv8.3 javascript Floating-point to Integer conversion instruction. Possible values of this parameter are: - 1, feature is implemented if ARMv8.3 is enabled. - 2, feature is implemented.
has_large_system_ext bool 0x0 Implement the ARMv8 Large System Extensions.
has_large_va int 0x0 Implement support for the extended 52-bit virtual addresses from ARMv8.2. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.2 is enabled. - 2, feature is implemented.
has_ldapur_stlur int 0x1 Implement support for LDAPR and STLR instructions with immediate offsets from ARMv8.4. Possible values of this parameter are: - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_ldm_stm_ordering_control int 0x0 Implement the SCTLR_ELx.LSMAOE (Load/Store Multiple Atomicity and Ordering Enable) and SCTLR_ELx,nTLSMD (no Trap Load/Store Multiple to Device) controls from ARMv8.2. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.2 is enabled. - 2, feature is implemented.
has_lrcpc bool 0x0 If true then it support the RCpc feature (ARMv8.3)
has_mpam int 0x0 Implement ARMv8.4 MPAM Registers and associated functionality. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_nested_virtualization int 0x1 Implement ARMv8.3 nested virtualization. Possible values of this parameter are: - 1, feature is implemented if ARMv8.3 is enabled. - 2, feature is implemented.
has_no_os_double_lock int 0x0 Do not implement the OS double-lock. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_non_context_synchronizing_exception_controls int 0x1 Implement cosmetic controls for whether exception entry and exit are context synchronizing events (SCTLR_ELx.{EIS,EOS}) from ARMv8.5. Possible values of this parameter are: - 1, feature is implemented if ARMv8.5 is enabled. - 2, feature is implemented.
has_pc_sample_based_profiling bool 0x1 If true, pc sample-based profiling is enabled.
has_pmu bool 0x1 Implement the optional Performance Monitors Extension.
has_pointer_authentication int 0x1 Implement ARMv8.3 pointer authentication. Possible values of this parameter are: - 1, feature is implemented if ARMv8.3 is enabled. - 2, feature is implemented.
has_prediction_invalidation_instructions int 0x1 Implement execution and data prediction invalidation from ARMv8.5 Possible values of this parameter are: - 1, feature is implemented if ARMv8.5 is enabled. - 2, feature is implemented.
has_pstate_dit int 0x1 Implement timing insensitivity of data processing instructions from ARMv8.4. Possible values of this parameter are: - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_pstate_pan int 0x1 Implement the PSTATE.PAN (Privileged Access Never) control from ARMv8.1 Possible values of this parameter are: - 1, feature is implemented if ARMv8.1 is enabled. - 2, feature is implemented.
has_pstate_uao int 0x1 Implement the PSTATE.UAO (User Access Override) control from ARMv8.2. Possible values of this parameter are: - 1, feature is implemented if ARMv8.2 is enabled. - 2, feature is implemented.
has_ras int 0x0 Implements the ARMv8 RAS Extension. 0 = NO_RAS, 1 = MINIMAL_RAS, 2 = FULL_RAS
has_ras_critical_error int 0x0 [DEPRECATED: Set CI field on first register in error_record_feature_register JSON instead] ARMv8.4 AArch64 RAS Critical Error is implemented or not. 0 - Feature Not Supported, 1 - Feature always enabled, 2 - Feature is controllable.
has_ras_double_fault int 0x1 Implement ARMv8.4 RAS Doublt Fault Extension. Possible values of this parameter are: - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_ras_fault_injection int 0x0 [DEPRECATED: Set INJ field on first register in error_record_feature_register JSON instead] Implement ARMv8.4 Standard Fault Injection mechanism. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_ras_timestamp int 0x0 [DEPRECATED: Set TS field on first register in error_record_feature_register JSON instead] ARMv8.4 AArch64 RAS Timestamp register is implemented or not. 0 - No Timestamp is recorded, 1 - Generic Timer timestamp is recorded, 2 - IMP DEF timestamp is recorded.
has_restriction_on_speculative_data_loaded int 0x1 Implements the ARMv8.5 security feature (Restrictions on the effects of speculation) Possible values of this parameter are: - 1, feature is implemented if ARMv8.5 is enabled. - 2, feature is implemented.
has_rndr int 0x0 Implement random number instructions to read from RNDR and RNDRSS random number registers from ARMv8.5. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.5 is enabled. - 2, feature is implemented.
has_rounding_doubling_multiply_add_subtract int 0x1 Implement the rounding doubling multiply add and subtract instructions from ARMv8.1 Possible values of this parameter are: - 1, feature is implemented if ARMv8.1 is enabled. - 2, feature is implemented.
has_secure_el2 int 0x1 Implement support for Secure EL2 Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_self_hosted_trace_extension int 0x1 Implement support for the Self-hosted Trace Extensions from ARMv8.4. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_small_page_table int 0x1 Implement small page table support which increases the maximum value of TxSZ field from ARMv8.4. Note: will be unimplemented only if both has_small_page_table=0x0 and has_secure_el2=0x0. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_software_lock bool 0x1 Implement software lock in memory-mapped CTI, PMU, and external debug interfaces
has_speculation_barrier_inst int 0x1 Implement speculation barrier instruction (SB) from ARMv8.5 Possible values of this parameter are: - 1, feature is implemented if ARMv8.5 is enabled. - 2, feature is implemented.
has_stage2_ap_speculative_update bool 0x0 If true, stage1 TTW can speculatively update stage2 AP bit
has_stage2_fwb int 0x1 Implement HCR_EL2.FWB, stage 2 control of memory types and cacheability Possible values of this parameter are: - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_stage2_xnx int 0x1 Implement the extended XN[1:0] stage 2 control from ARMv8.2. Possible values of this parameter are: - 1, feature is implemented if ARMv8.2 is enabled. - 2, feature is implemented.
has_statistical_profiling bool 0x1 Whether Statistical Based Profiling is implemented
has_supersections bool 0x1 Whether VMSAv8-32 supersection to support more than 32-bit PA using short descriptor is implemented.
has_synchronous_load_atomics bool 0x1 Report asynchronous abort due to unsupported load atomics as synchronous
has_synchronous_store_atomics bool 0x0 Report asynchronous abort due to unsupported store atomics as synchronous
has_tlb_conflict_abort bool 0x0 Detected inconsistent TLB content generate aborts.
has_tlbi_range int 0x1 Implement support for TLB Range Maintenance instructions (TLBI RVAE1, etc) from ARMv8.4. Possible values of this parameter are: - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_tlbi_to_outer_shareable int 0x1 Implement support for TLB Maintenance instructions that extend to the Outer Shareable domain (TLBI VAE1OS, etc) from ARMv8.4. Possible values of this parameter are: - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_tlbi_ttl int 0x1 Implement support for the TTL level hint in by-address TLB Maintenance instructions from ARMv8.4. Possible values of this parameter are: - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_unaligned_single_copy_atomicity int 0x1 Implement support for SCTLR_ELx.nAA from ARMv8.4, and A64 atomic, exclusive and acquire/release instructions accessing unaligned bytes inside a 16byte window will not generate alignment fault. Possible values of this parameter are: - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_unsupported_exclusive_fault bool 0x1 Report unsupported exclusive access with Unsupported Exclusive fault status (otherwise use external abort)
has_v8_4_debug_extension int 0x1 Implement ARMv8.4 debug extensions Possible values of this parameter are: - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_v8_4_pmu_extension int 0x1 Implement PMU extension from ARMv8.4. Possible values of this parameter are: - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_v8_5_debug_over_power_down int 0x0 Implement ARMv8.5 Debug over powerdown Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.5 is enabled. - 2, feature is implemented.
has_v8_5_pmu_extension int 0x1 Implement PMU extension from ARMv8.5. Possible values of this parameter are: - 1, feature is implemented if ARMv8.5 is enabled. - 2, feature is implemented.
has_v8_5_spe_extension int 0x1 Implement SPE extension from ARMv8.5 Possible values of this parameter are: - 1, feature is implemented if ARMv8.5 is enabled. - 2, feature is implemented.
has_vncr_el2 int 0x1 Implement support for nested virtualization enhancements from ARMv8.4. Possible values of this parameter are: - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
has_writebuffer bool 0x0 Implement write accesses buffering before L1 cache. May affect ext_abort behaviour.
hcptr_tta_behaviour int 0x2 Behaviour of HCPTR.TTA when there is no CP14 ETM interface. 0, RAZ/WI. 1, RAO/WI. 2, stateful.
hcr_swio_res1 bool 0x0 Whether HCR.SWIO and/or HCR_EL2.SWIO are RES1.
hsr_uncond_cc bool 0x0 Condition codes reported in HSR as AL if it passes
icache-hit_latency int 0x0 L1 I-Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when icache-state_modelled=true.
icache-log2linelen int 0x0 If nonzero, Log2 of the instruction cache line length in bytes (valid values in range 4-8). Otherwise the value of cache-log2linelen is used.
icache-maintenance_latency int 0x0 L1 I-Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when icache-state_modelled=true.
icache-miss_latency int 0x0 L1 I-Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when icache-state_modelled=true.
icache-nprefetch int 0x1 Number of next sequential instruction cache lines to prefetch. This is only used when icache-prefetch_enabled=true.
icache-prefetch_enabled bool 0x0 Enable simulation of instruction cache prefetching. This is only used when icache-state_modelled=true.
icache-prefetch_level int 0x0 0 based cache level at which instructions are pre-fetched. This is only used when icache-prefetch_enabled=true.
icache-read_access_latency int 0x0 L1 I-Cache timing annotation latency for read accesses given in ticks per access (of size icache-read_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if icache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, this is only used when icache-state_modelled=true.
icache-read_bus_width_in_bytes int 0x8 L1 I-Cache read bus width in bytes used to calculate per-access timing annotations
icache-read_latency int 0x0 L1 I-Cache timing annotation latency for read accesses given in ticks per byte accessed.icache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when icache-state_modelled=true.
icache-size int 0x8000 L1 I-Cache size in bytes.
icache-state_modelled bool 0x0 Set whether I-cache has stateful implementation
icache-ways int 0x2 L1 I-Cache number of ways (sets are implicit from size).
ignore_DBGPRCR_CWRR bool 0x0 Ignore writes to the deprecated DBGPRCR.CWRR bit.
ignore_access_flag_update_by_at_ops bool 0x0 If true, AT operations do not update access flag
imp_def_functionality_behaviour int 0x0 Behaviour of IMPLEMENTATION DEFINED registers and system instructions. 0, UNDEF. 1, RAZ/WI.
impdef_regs_and_unpred_from_implementation string "" Configure implementation defined registers and unpredictable behaviour to match the specified implementation. Requires a license for the selected implementation model. Use ARM_Cortex-A<num> or ARM_<codename> for licensed pre-release cores.
independent_cache_control_traps int 0x0 Implement Independent Cache Control traps from ARMv8.5. 0, NO_SUPPORT. 1, SUPPORTED_BUT_NOT_FOR_TLB_MAINTENANCE_INSTRUCTIONS. 2, FULL_SUPPORT.
instruction_tlb_size int 0x0 Number of stage1+2 itlb entries (or 0 for unified ITLB+DTLB)
is_first_pcsr_sample_ignored bool 0x0 If true, First read of PMPCSR register after reset returns 0xFFFFFFFF
is_uniprocessor bool 0x0 Value for the U bit in MPIDR. true disables L1 cache coherency protocols
itd_conditional_instructions_are_32bit bool 0x0 When SCTLR_ELx.ITD=1, an IT instruction plus a T16 instruction are considered a single 32bit conditional instruction.
jidr_is_undef_at_el0 bool 0x0 If true, JIDR register access is UNDEF at EL0
l2cache-hit_latency int 0x0 L2 Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when l2cache-state_modelled=true.
l2cache-maintenance_latency int 0x0 L2 Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when dcache-state_modelled=true.
l2cache-miss_latency int 0x0 L2 Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when l2cache-state_modelled=true.
l2cache-read_access_latency int 0x0 L2 Cache timing annotation latency for read accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l2cache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, this is only used when l2cache-state_modelled=true.
l2cache-read_bus_width_in_bytes int 0x8 L2 Cache read bus width in bytes used to calculate per-access timing annotations
l2cache-read_latency int 0x0 L2 Cache timing annotation latency for read accesses given in ticks per byte accessed.l2cache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when l2cache-state_modelled=true.
l2cache-size int 0x80000 L2 Cache size in bytes.
l2cache-snoop_data_transfer_latency int 0x0 L2 Cache timing annotation latency for received snoop accesses that perform a data transfer given in ticks per byte accessed. This is only used when dcache-state_modelled=true.
l2cache-snoop_issue_latency int 0x0 L2 Cache timing annotation latency for snoop accesses issued by this cache in total ticks. This is only used when dcache-state_modelled=true.
l2cache-ways int 0x10 L2 Cache number of ways (sets are implicit from size).
l2cache-write_access_latency int 0x0 L2 Cache timing annotation latency for write accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l2cache-write_latency is set. This is only used when l2cache-state_modelled=true.
l2cache-write_bus_width_in_bytes int 0x8 L2 Cache write bus width in bytes used to calculate per-access timing annotations
l2cache-write_latency int 0x0 L2 Cache timing annotation latency for write accesses given in ticks per byte accessed. l2cache-write_access_latency must be set to 0 for per-byte latencies to be applied. This is only used when l2cache-state_modelled=true.
l3cache-hit_latency int 0x0 L3 Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when l3cache-state_modelled=true.
l3cache-miss_latency int 0x0 L3 Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when l3cache-state_modelled=true.
l3cache-mpamf.bwa_width_ns int 0x10 L3 Cache width of MPAM bandwidth allocation fields for non-secure accesses.
l3cache-mpamf.bwa_width_s int 0x10 L3 Cache width of MPAM bandwidth allocation fields for secure accesses.
l3cache-mpamf.cmax_width_ns int 0x0 L3 Cache number of fractional bits in MPAM cache capacity partition control for non-secure accesses. Only the register interface is implemented - the control is NOT FUNCTIONAL.
l3cache-mpamf.cmax_width_s int 0x0 L3 Cache number of fractional bits in MPAM cache capacity partition control for secure accesses. Only the register interface is implemented - the control is NOT FUNCTIONAL.
l3cache-mpamf.cpbm_width_ns int 0x0 L3 Cache width of MPAM cache portion bitmap for non-secure accesses. If 0, the feature is not implemented, and all ways are available.
l3cache-mpamf.cpbm_width_s int 0x0 L3 Cache width of MPAM cache portion bitmap for secure accesses. If 0, the feature is not implemented, and all ways are available.
l3cache-mpamf.csu_num_mon_ns int 0x0 L3 Cache number of MPAM cache storage usage monitors for non-secure accesses.
l3cache-mpamf.csu_num_mon_s int 0x0 L3 Cache number of MPAM cache storage usage monitors for secure accesses.
l3cache-mpamf.has_prop_ns bool 0x0 Enable memory bandwidth proportional stride control for non-secure accesses. Only the register interface is implemented - the control is NOT FUNCTIONAL.
l3cache-mpamf.has_prop_s bool 0x0 Enable memory bandwidth proportional stride control for secure accesses. Only the register interface is implemented - the control is NOT FUNCTIONAL.
l3cache-size int 0x0 L3 Cache size in bytes.
l3cache-ways int 0x10 L3 Cache number of ways (sets are implicit from size).
log2_of_memory_tags_in_bulk_access int 0x2 Number of memory tags to be accessed by LDGV and STGV instructions
max_32bit_el int 0x3 Maximum exception level supporting AArch32 modes.
memory.acp.AxCACHE_mask int 0x0 Used with memory.acp.AxCACHE_pattern to define which memory types the ACP port accepts. All transactions which do not satisfy (AxCACHE & mask) == pattern will abort.
memory.acp.AxCACHE_pattern int 0x0 Used with memory.acp.AxCACHE_mask to define which memory types the ACP port accepts. All transactions which do not satisfy (AxCACHE & mask) == pattern will abort.
memory.l2_cache.is_inner_cacheable bool 0x1 L2 cache obeys inner cacheable attributes (rather than outer cacheable attributes)
memory.l2_cache.is_inner_shareable bool 0x1 L2 cache obeys inner shareable attributes (rather than outer sharaable attributes)
memory_tagging_support_level int 0x0 Specify the memory tagging extension support level: 0, not implemented. 1, instructions and registers only are implemented. 2, implemented.
mixed_endian int 0x1 Implement support for mixed endianness. 0, not supported. 1, supported at all exception levels. 2, supported at EL0 only.
mpam_has_hcr bool 0x0 MPAM Whether MPAMIDR_EL1 HAS_HCR bit is set or clear
mpam_max_partid int 0xffff MPAM Maximum PARTID Supported
mpam_max_pmg int 0xff MPAM Maximum PMG Supported
mpam_max_vpmr int 0x0 MPAM Maximum VPMR Supported
mpidr_layout int 0x0 Layout of MPIDR. 0 AFF0 is CPUID, 1 AFF1 is CPUID
mvbar_reset_is_rvbar bool 0x1 If true then the reset value of MVBAR is RVBAR, if false the reset value is UNKNOWN.
non_secure_vgic_alias_when_ns_only int 0x0 If ! has_el3 and only non-secure side exists, then the normal position of the VGIC is a secure alias. If this parameter is non-zero then in addition a non-secure alias of the VGIC will be placed at this position (aligned to 32 KB).
num_loregion_descriptors int 0x0 Number of Limited Ordering Region descriptors implemented (if ARM v8.1 extensions are implemented)
num_loregions int 0x0 Number of Limited Ordering Regions implemented excluding background region (if ARM v8.1 extensions are implemented)
number_of_error_records int 0x0 Cores Number of Error records supported for RAS
optimal_alignment_size int 0x1 Alignment boundary which does not incur additional performance penalty from ARMv8.5. - 1, architectural misalignment is used to set PMU event LDST_ALIGN_LAT and SPE event E[11] - 2, access crossing 4 byte boundary is used to set PMU event LDST_ALIGN_LAT and SPE event E[11] - 3, access crossing 8 byte boundary is used to set PMU event LDST_ALIGN_LAT and SPE event E[11] ... - 12, access crossing 4 Kbyte boundary is used to set PMU event LDST_ALIGN_LAT and SPE event E[11]
output_attributes string "ExtendedID[62:55]=MPAM_PMG, ExtendedID[54:39]=MPAM_PARTID, ExtendedID[38]=MPAM_NS" User-defined transform to be applied to bus attributes like MasterID, ExtendedID or UserFlags. Currently, only works for MPAM Attributes encoding into bus attributes.
page_based_hardware_attributes int 0x0 Implement the page based hardware attributes from ARMv8.2. This parameter indicates which page table bits are available for hardware, where bits[3:0] correspond to PTE[62:59] and to TCR_ELx.HWUnyy.
pmu-num_counters int 0x8 Number of pmu counters implemented
pmu_has_chain_event bool 0x1 PMU (if present) implements event number 0x1e, CHAIN.
pseudo_fault_generation_feature_register string "" ARMv8.4 Standard Pseudo-fault generation feature register values. JSON schema for the parameter value is: [{"OF":false,"UC":false,"UEU":false,"UER":false,"UEO":false,"DE":false,"CE":0x0,"CI":false,"ER":false,"PN":false,"AV":false,"MV":false,"SYN":false,"R":false},other_psuedo-fault_generating_features_register_values]. Where OF, UC, UEU, UER, UEO, DE, CI, ER, PN, AV, MV, SYN, and R have valid false(NOT_SUPPORTED) and true(FEATURE_CONTROLLABLE), where CE can have 0(NOT_SUPPORTED), 1(NONSPECIFIC_CE_SUPPORTED) and 3(TRANSIENT_OR_PERSISTENT_CE_SUPPORTED). Effective only when ERXFR's INJ field allows it or has_ras_fault_injection is true.
pstate_ssbs_type int 0x0 Implement speculative store bypass safe feature from ARMv8.5. 0, Not supported. 1, Supported without MSR/MRS access to SSBS. 2, fully supported.
ptw_latency int 0x0 Page table walker latency for TA (Timing Annotation), expressed in simulation ticks
ras_frac int 0x0 0, No additional feature implemented. 1, Additional ERXMISC*, ERXPFG* registers and FaultInjection trap from RAS v1.1. implemented
register_reset_data int 0x0 Data used to fill register bits when they become UNKNOWN at reset.
report_iside_cmo_ifsr bool 0x1 fault info for an iside cache maintenance operation is reported in the IFSR
restriction_on_speculative_execution int 0x0 Implements the ARMv8.5 security feature (Restrictions on the effects of speculation): 0: No disclosure whether branch targets trained in one context can affect speculative execution in a different context, 1: Branch targets trained in one context cannot affect speculative execution in a different hardware described context (SCXTNUM_ELx not supported), 2: Branch targets trained in one context cannot affect speculative execution in a different hardware described context (SCXTNUM_ELx supported)
rmr_always_implemented bool 0x0 Always implement RMR_ELx, RMR, or HRMR at the highest implemented exception level, even if that exception level cannot use both AArch32 and AArch64.
rndr_rndrrs_seed int 0x0 Initial seed for random engine used in RNDR register
scheduler_mode int 0x0 Control the interleaving of instructions in this processor. 0, default long quantum. 1, low latency mode, short quantum and signal checking. 2, lock-breaking mode, long quantum with additional context switches near load-exclusive instructions.
scr_nET_writeable bool 0x0 Whether SCR.nET is writeable. Writing to it is purely cosmetic (nET behavior not implemented)
scramble_unknowns_at_reset bool 0x1 Will fill in unknown bits in registers at reset with register_reset_data
spsr_el3_is_mapped_to_spsr_mon bool 0x1 Whether SPSR_EL3 is mapped to AArch32 register SPSR_mon
stage12_tlb_size int 0x80 Number of stage1+2 tlb entries.
stage1_tlb_size int 0x0 Number of stage1 only tlb entries.
stage1_walkcache_size int 0x0 Number of stage1 only walk cache entries.
stage2_tlb_size int 0x0 Number of stage2 only tlb entries.
stage2_walkcache_size int 0x0 Number of stage2 only walk cache entries.
statistical_profiling_buffer_alignment int 0x1 Statistical profiling alignment constraint for sample buffer
statistical_profiling_random_interval_is_separate bool 0x0 Statistical profiling random interval gets added to the main timer interval(false) or (true) runs as separate timer
statistical_profiling_recommended_min_sampling int 0x100 Statistical profiling recommended minimum sampling interval
strex_fail_can_hit_watchpoint bool 0x0 If true, a strex fail can hit watchpoint
supports_multi_threading bool 0x0 Sets the MPIDR.MT bit. Setting this to true hints the the cluster is multi-threading compatible
take_ccfail_tsc_trap bool 0x0 When take_ccfail_undef=1 this prameter controls whether or not an SMC instruction that is trapped by HCR_EL2.TSC but fails its condition code check generates a trap to EL2.
take_ccfail_undef bool 0x1 UNDEF exception is taken even if condition code check fails
tcr_ps_reserved_value_size int 0x0 Physical size treated when TCR.(I)PS is programmed with a reserved value. 0, 48 bits. 1, 52 bits. The parameter value is treated 0 if LPA is not supported.
tdosa_traps_osdlr_if_no_os_double_lock bool 0x1 MDCR_EL*.TDOSA enables trap on OSDLR_EL1 and DBGOSDLR when OS double-lock is not implemented.
tidcp_traps_el0_undef_imp_def bool 0x1 TIDCP has priority over UNDEF for accesses to IMPLEMENTATION DEFINED functionality from EL0
tlb_latency int 0x0 TLB latency for TA (Timing Annotation), expressed in simulation ticks
trace_has_sysreg_access bool 0x1 ETM trace registers support access via system registers
trace_physical_registers_when_host_virtualisation_enabled int 0x0 When host virtualisation is enabled, trace sysreg accesses to physical register accessed (0=disabled, 1=Trace only ELR/SPSR_EL1 as ELR/SPSR_EL2, 2=Trace all redirected registers as physical registers
trap_reserved_group3_id_regs bool 0x0 Whether setting HCR_EL2.TID3 traps reserved group3 id registers.
treat-dcache-cmos-to-pou-as-nop bool 0x0 Whether dcache invalidation to the point of unification is required for instruction to data coherence. true - Invalidate operations not required
treat-dcache-invalidate-as-clean-invalidate bool 0x0 Treat data cache invalidate operations as clean and invalidate.
treat_pld_as_nop bool 0x0 If true, treat PLD as NOP.
treat_pli_as_nop bool 0x0 If true, treat PLI as NOP.
treat_wfi_wfe_as_nop bool 0x0 If true, never go into wait state for WFI or WFE instructions.
truncate_pc_on_illegal_exception_return_to_aarch32 bool 0x1 On Illegal ERET to AArch32, truncate PC to 32-bits
unification-level int 0x1 Level of Unification Inner Shareable for the cache hierarchy
unification-uniprocessor-level int 0x1 Level of Unification Uniprocessor for the cache hierarchy
unpred_edscr_rw_unknown_bits_read_as_1 bool 0x0 Unknown(x) bits in RW field in EDSCR are read as 1 instead of 0.
unpred_load_single_reg_overlap_with_wb int 0x0 Constrained unpredictable behaviours for single load with writeback(might impact certain load pair instructions) 0 Constraint_WBSUPPRESS, 1 Constraint_UNDEF, 2 Constraint_NOP
unpred_mrsmsr_currentlymapped_undef bool 0x0 UNPREDICTABLE register access (accessible from current mode using different instruction) modeled as NOP when false and UNDEF when true
unpred_mrsmsr_protfailed_undef bool 0x0 UNPREDICTABLE register access (not accessible from current PL and security state) modeled as NOP when false and UNDEF when true
unpred_store_exclusive_base_overlap int 0x0 Constrained unpredictable behaviours for store exclusive when s==n. 0 Constraint_NONE, 1 Constraint_UNDEF, 2 Constraint_NOP
unpred_store_pair_and_single_reg_overlap_with_wb int 0x0 Constrained unpredictable behaviours for pair and single store with writeback(doesn't cover store exclusive) 0 Constraint_NONE, 1 Constraint_UNDEF, 2 Constraint_NOP
unpred_tsize_aborts bool 0x0 Behaviour when TSize is out of range. 0, force into range. 1, translation fault, forces unpred_tsize_pamax_aborts to 1.
unpred_tsize_pamax_aborts bool 0x0 Behaviour when stage 2 TSize exceeds the physical address size (or 40bits, from AArch32). 0, force into range. 1, translation fault. Ignored if unpred_tsize_aborts is 1.
unpred_vncr_el2_ress_mismatch int 0x0 Constrained unpredictable choices when bits marked as RESS do not all have the same value for VNCR_EL2 - 0, Generating an EL2 translation regime translation abort on use of the VNCR_EL2 register - 1, Reserved sign exteneded bits of VNCR_EL2 are same as bit[52] or bit[48] based on if large VA is supported or not, for all purposes other than reading back the register
unpredictable_exclusive_abort_memtype int 0x0 Cause MMU abort if exclusive access is not supported in certain memory type (0=exclusives allowed in all memory types, 1=exclusives abort in Device memory types, 2=exclusives abort in any type other than WB inner cacheable)
unpredictable_hvc_behaviour int 0x0 HVC unpredictable behaviour. 0, UNDEF. 1, NOP.
unpredictable_smc_behaviour int 0x0 SMC unpredictable behaviour. 0, UNDEF. 1, NOP.
unsupported_atomic_fault_type int 0x0 Type of fault reported on unsupported atomic access. 0 = external abort if any reported by interconnect, 1 = precise unsupported atomic fault, 2 = precise external abort.
use_mte_eac_02_instructions_encoding bool 0x1 Use new MTE Intructions encoding since MTE spec EAC 0.2 in ARMv8.5.
use_rosetta_disass int 0x1 Use Rosetta disassembly library. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
use_tlb_contig_hint bool 0x0 Translation table entries with the contiguous hint bit set generate large TLB entries.
walk_cache_latency int 0x0 Walk cache latency for TA (Timing Annotation), expressed in simulation ticks
warn_unpredictable_in_v7 bool 0x1 If true, behaviour which is unpredictable in V7 yet is predictable in V8 will produce a warning
watchpoint-log2secondary_restriction int 0x0 log2 size of secondary restriction of FAR/EDWAR possible values on watchpoint hit for load/store operations.

Table 3-71 Parameters for ARMAEMv8-A_MP

Name Type Default value Description
cpu0.CFGEND bool 0x0 Endianness configuration at reset. 0, little endian. 1, big endian.
cpu0.CONFIG64 bool 0x1 Register width configuration at reset. 0, AArch32. 1, AArch64.
cpu0.CP15SDISABLE bool 0x0 Initialize to disable access to some CP15 registers
cpu0.CP15SDISABLE2 bool 0x0 Initialize to disable access to some CP15 registers
cpu0.CRYPTODISABLE bool 0x0 Disable cryptographic features.
cpu0.DCZID-log2-block-size int 0x8 Log2 of the block size cleared by DC ZVA instruction (as read from DCZID_EL0).
cpu0.DCZVA_single_write bool 0x0 Execute the DCZVA as a single write
cpu0.MPIDR-override int 0x0 Override of MPIDR value. If nonzero will override the MT, cluster and CPU ID bits in MPIDR.
cpu0.RVBAR int 0x0 Value of RVBAR_ELx register.
cpu0.SMPnAMP bool 0x1 Enable broadcast messages necessary for correct SMP operation at reset.
cpu0.TEINIT bool 0x0 Instruction set state when resetting into AArch32. 0, A32. 1, T32.
cpu0.VINITHI bool 0x0 Reset value of SCTLR.V.
cpu0.ase-present bool 0x1 Set whether the model has been built with NEON support
cpu0.clock_divider int 0x1 Clock divider ratio for asymmetric MP clocking.
cpu0.clock_multiplier int 0x1 Clock divider ratio for asymmetric MP clocking.
cpu0.crypto_aes int 0x2 AES instructions supported (requires CryptoPlugin to be loaded). 0, not implemented. 1, AES instructions implemented. 2, AES and PMULL instructions implemented.
cpu0.crypto_sha1 int 0x1 SHA-1 instructions supported (requires CryptoPlugin to be loaded). 0, not implemented. 1, SHA1 instructions implemented.
cpu0.crypto_sha256 int 0x1 SHA-256 instructions supported (requires CryptoPlugin to be loaded). 0, not implemented. 1, SHA256 instructions implemented.
cpu0.crypto_sha3 int 0x0 Implement ARMv8.4 SHA-3 instructions (requires CryptoPlugin to be loaded). Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
cpu0.crypto_sha512 int 0x0 Implement ARMv8.4 SHA-512 instructions (requires CryptoPlugin to be loaded). Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
cpu0.crypto_sm3 int 0x0 Implement ARMv8.4 SM-3 instructions (requires CryptoPlugin to be loaded). Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
cpu0.crypto_sm4 int 0x0 Implement ARMv8.4 SM-4 instructions (requires CryptoPlugin to be loaded). Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.4 is enabled. - 2, feature is implemented.
cpu0.cti-intack_mask int 0x1 Set bits represent that the corresponding trigger requires software acknowledge via CTIINTACK
cpu0.cti-number_of_claim_bits int 0x0 Number of implemented bits in CTICLAIMSET
cpu0.cti-number_of_triggers int 0x8 Number of cti event triggers
cpu0.enable_crc32 int 0x0 CRC32 instructions supported. 0, not implemented. 1, CRC32 instructions implemented.
cpu0.enable_trace_special_hlt_imm16 bool 0x0 Enable usage of parameter trace_special_hlt_imm16
cpu0.etm-present bool 0x1 Set whether the model has ETM support
cpu0.force-fpsid bool 0x0 Override the FPSID value
cpu0.force-fpsid-value int 0x0 Value to override the FPSID value to
cpu0.has_hcptr_tase bool 0x1 If false, HCPTR.TASE is RES0
cpu0.max_code_cache_mb int 0x100 Maximum size of the simulation code cache (MiB). For platforms with more than 2 cores this limit will be scaled down. (e.g 1/8 for 16 or more cores)
cpu0.min_sync_level int 0x0 Force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
cpu0.number-of-breakpoints int 0x10 Number of breakpoints.
cpu0.number-of-context-breakpoints int 0x10 Number of breakpoints that are context aware.
cpu0.number-of-watchpoints int 0x10 Number of watchpoints.
cpu0.operation_bandwidth int 0x1 Operation width for ARMv8.4 PMU extension
cpu0.semihosting-A32_HLT int 0xf000 A32 HLT number for semihosting calls.
cpu0.semihosting-A64_HLT int 0xf000 A64 HLT number for semihosting calls.
cpu0.semihosting-ARM_SVC int 0x123456 A32 SVC number for semihosting calls.
cpu0.semihosting-T32_HLT int 0x3c T32 HLT number for semihosting calls.
cpu0.semihosting-Thumb_SVC int 0xab T32 SVC number for semihosting calls.
cpu0.semihosting-cmd_line string "" Command line available to semihosting calls.
cpu0.semihosting-cwd string "" Base directory for semihosting file access.
cpu0.semihosting-enable bool 0x1 Enable semihosting SVC/HLT traps.
cpu0.semihosting-heap_base int 0x0 Virtual address of heap base.
cpu0.semihosting-heap_limit int 0xf000000 Virtual address of top of heap.
cpu0.semihosting-prefix bool 0x0 Prefix semihosting output with target instance name
cpu0.semihosting-stack_base int 0x10000000 Virtual address of base of descending stack.
cpu0.semihosting-stack_limit int 0xf000000 Virtual address of stack limit.
cpu0.semihosting-stderr_istty bool 0x1 Result for semihost istty call when argument is stderr
cpu0.semihosting-stdin_istty bool 0x1 Result for semihost istty call when argument is stdin
cpu0.semihosting-stdout_istty bool 0x1 Result for semihost istty call when argument is stdout
cpu0.semihosting-use_stderr bool 0x0 Send stderr from the simulated process to host stderr
cpu0.trace_special_hlt_imm16 int 0xf000 For this HLT number, IF enable_trace_special_hlt_imm16=true, skip performing usual HLT execution but call MTI trace if registered
cpu0.unpredictable_WPMASKANDBAS int 0x1 Constrained unpredictable handling of watchpoints when mask and BAS fields specified. 0, IGNOREMASK. 1, IGNOREBAS (default). 2, REPEATBAS8. 3, REPEATBAS.
cpu0.vfp-enable_at_reset bool 0x0 Enable VFP in CPACR, CPPWR, NSACR at reset. Warning: Arm recommends going through the implementation's suggested VFP power-up sequence!
cpu0.vfp-present bool 0x1 Set whether the model has VFP support
cpu0.vfp-traps bool 0x1 Implement support for trapping floating-point exceptions
cpu0.vfp-traps-show-all bool 0x0 Report all trapped floating-point exceptions in the syndrome when a combination occurs.
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