3.3.1 ClockDivider

A ClockDivider is a library component that takes a ClockSignal on its input port (which could come from the output of a MasterClock, or from another ClockDivider), and generates a new ClockSignal on its output port, representing a clock frequency that is related to the input clock by the ratio of the multiply and divide parameters. This model is written in C++.

ClockDivider - about

This component uses a configurable ratio to convert the ClockSignal rate at its input to a new ClockSignal rate at its output. Changes to the input rate or ratio take effect immediately and clocking components dependent on the output rate continue counting at the new rate.

This component does not normally incur a runtime performance cost. However, reprogramming the clock rate causes all related clocks and timers to be recalculated.

For examples of the use of ClockDividers, see the VEMotherBoard.lisa component in the $PVLIB_HOME/examples/LISA/FVP_VE/LISA directory of your Fast Models distribution.

Table 3-63 Ports

Name Protocol Type Description
clk_in ClockSignal Slave Input clock signal, coming from a MasterClock or another ClockDivider.
clk_out ClockSignal Master Clock signal generated by this ClockDivider.
rate 2.2.2 ClockRateControl protocol Slave Permits you to dynamically change the clock divider ratio.
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