3.10.35 PL022_SSP

ARM PrimeCell Synchronous Serial Port(PL022). This model is written in LISA+.

PL022_SSP contains the following CADI targets:

  • PL022_SSP

PL022_SSP contains the following MTI components:

Differences with hardware

Although the PL022_SSP component has clock input, it is not internally clock-driven. This is different to the hardware.


This component is a preliminary release. It is provided as-is with the VE reference platform model, and is not a fully-supported peripheral.

Table 3-362 Ports

Name Protocol Type Description
clk ClockSignal Slave Main PrimeCell SSP clock input.
clkin ClockSignal Slave PrimeCell SSP clock input.
clkout ClockSignal Master Clock output.
intr 2.7.2 Signal protocol Master Interrupt signaling.
pvbus PVBus Slave Slave port for connection to PV bus master/decoder.
rorintr 2.7.2 Signal protocol Master Receive overrun interrupt.
rtintr 2.7.2 Signal protocol Master Receive timeout interrupt. We don't implement time out interrupt.
rx_dma_port 2.4.11 PL080_DMAC_DmaPortProtocol protocol Master PrimeCell SSP receive DMA port.
rxd 2.7.4 Value protocol Slave PrimeCell SSP receive data.
rxintr 2.7.2 Signal protocol Master Receive FIFO service request port.
tx_dma_port 2.4.11 PL080_DMAC_DmaPortProtocol protocol Master PrimeCell SSP transmit DMA port.
txd 2.7.4 Value protocol Master PrimeCell SSP transmit data.
txintr 2.7.2 Signal protocol Master Transmit FIFO service request.
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