5.15.9 TLB trace

If enabled, this source traces TLB entries that are filled and evicted by the processor.

Output syntax:

<time> <scale> <cpu> [TLB|WALKCACHE] FILL <id> <size> <virtualregime>:<paddr> {<memtype>} {<attr>=<value>}+
<time> <scale> <cpu> [TLB|WALKCACHE] EVICT <id> <size> <virtualregime>
<time>

Timestamp (decimal value).

<scale>

Unit for <time>. clk indicates that the timestamp is not related to real time, but an increasing count.

<cpu>

Processor, or other component, that gave the instruction.

<id>
Identifies which TLB or walk cache to trace.
<size>
Size of the region being mapped.
<virtualregime>
Virtual address and regime of the region being mapped, formatted according to the common virtual regime definition.
<paddr>
Physical base address of mapped region, formatted according to the common address definition.
<memtype>
For TLB entries, the memory type of the result. One of the following options:
Device-[G|nG][R|nR][E|nE] {(<alias>)}
Device memory, where:
[G|nG]
Gathering or nongathering.
[R|nR]
Reordering or nonreordering.
[E|nE]
Early write acknowledgement or not.
<alias>
Device-nGnRnE was previously known as StronglyOrdered.
Normal [NonShareable|Shareable] Inner=<cachetype> Outer=<cachetype>
Normal memory, where:
[NonShareable|Shareable]
Shareability
<cachetype>
[NonCacheable|WriteBack|WriteThrough]{NonReadAllocate}{Non}{WriteAllocate}
[NonCacheable|WriteBack|WriteThrough]
Cacheability
{NonReadAllocate}
For cacheable memory, Read allocate hint. (Read allocate is assumed if not specified.)
{Non}{WriteAllocate}
For cacheable memory, Write allocate hint.
Non-ConfidentialPDF file icon PDF version100964_1161_00_en
Copyright © 2014–2019 Arm Limited or its affiliates. All rights reserved.