3.4.21 ARMCortexA7x1CT

ARMCortexA7x1CT CPU component. This model is written in C++ and models version r0p0 of the RTL.

ARMCortexA7x1CT contains the following CADI targets:

  • ARM_Cortex-A7
  • Cluster_ARM_Cortex-A7
  • PVCache
  • TlbCadi

ARMCortexA7x1CT contains the following MTI components:

Note:

  • The following components also exist:

    • ARMCortexA7x2CT.
    • ARMCortexA7x3CT.
    • ARMCortexA7x4CT.
  • The per-core parameters are preceded by cpun., where n identifies the core (0-3).

Differences between the CT model and RTL implementations

This component has the following differences from the corresponding revision of the RTL implementation:

  • The GIC does not respect the CFGSDISABLE signal. This leads to some registers wrongly being accessible.
  • The Broadcast Translation Lookaside Buffer (TLB) or cache operations in this model do not cause other cores in the cluster that are asleep because of Wait For Interrupt (WFI) to wake up.
  • It ignores the RR bit in the SCTLR.
  • It implements the Power Control Register in the system control coprocessor but writing to it does not change the behavior of the model.
  • It does not implement ETM registers.
  • It does not support the Cortex®‑A7 mechanism to read the internal memory that the Cache and TLB structures use through the implementation defined region of the system coprocessor interface.

Debug features

All core, VFP, CP14, and CP15 registers are visible in the debugger. All CP14 debug registers are implemented.

This component directly supports single-address unconditional instruction breakpoints, unconditional instruction address range breakpoints, and single-address unconditional data breakpoints. The debugger might augment these with more complex combinations of breakpoints.

The model does not support CADI exception breakpoints. Instead, it implements exception breakpoints as register breakpoints on pseudoregisters, named after the exceptions, in the Vectors register group.

This component presents three 4GB views of virtual address space: hypervisor, secure, and non-secure.

ACE limitation

AXI Coherency Extensions (ACE) are extensions to AXI4 that support system-level cache-coherency between multiple clusters. The ACE cache models in the Cortex‑A15 and the Cortex‑A7, and the ACE support in the CCI-400 have the limitation that they only process one transaction at a time. Normally, the simulation processes each transaction to completion before allowing any master to generate another transaction. However, in the following situation the simulation might fail. If a SystemC bus slave calls wait() while it is processing a transaction, this call might allow another master to issue another transaction that passes through the CCI-400 or the Cortex‑A15/Cortex‑A7 caches. This situation could happen if a SystemC bus master running in another thread is connected to one of the ACE-lite ports on the CCI-400.

Additional parameter information

ase-present
The ase-present and vfp-present parameters configure the synthesis options:
vfp present and ase present
NEON and VFPv4-D32 supported.
vfp present and ase not present
VFPv4-D16 supported.
vfp not present and ase present
Illegal. Forces vfp-present to true so model has NEON and VFPv4-D32 support.
vfp not present and ase not present
Model has neither NEON nor VFPv4-D32 support.
PERIPHBASE
If you are using the ARMCortexA7xnCT component on a VE model platform, this parameter is set automatically to 0x2C000000 and is not visible in the parameter list.
vfp-enable_at_reset
This is a model-specific behavior with no hardware equivalent.

Table 3-133 Ports

Name Protocol Type Description
CNTHPIRQ[4] 2.7.2 Signal protocol Master Outputs of the generic timers.
CNTPNSIRQ[4] 2.7.2 Signal protocol Master Outputs of the generic timers.
CNTPSIRQ[4] 2.7.2 Signal protocol Master Outputs of the generic timers.
CNTVIRQ[4] 2.7.2 Signal protocol Master Outputs of the generic timers.
axierrirq 2.7.2 Signal protocol Master Imprecise aborts from the L2 are signaled by pulsing this pin, typically they are connect to an interrupt controller.
broadcastcachemaint 2.7.2 Signal protocol Slave Enable broadcasting of cache maintenance operations to downstream caches.
broadcastinner 2.7.2 Signal protocol Slave Enable broadcasting of Inner Shareable transactions.
broadcastouter 2.7.2 Signal protocol Slave Enable broadcasting of Outer Shareable transactions.
cfgend[4] 2.7.2 Signal protocol Slave This signal controls the SCTLR.EE bit.
cfgsdisable 2.7.2 Signal protocol Slave This signal disables write access to some secure Interrupt Controller registers.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
clusterid 2.7.4 Value protocol Slave This port sets the value in the CLUSTERID field (bits[11:8]) of the MPIDR.
cntvalueb 2.6.1 CounterInterface protocol Slave Interface to SoC level counter module.
cp15sdisable[4] 2.7.2 Signal protocol Slave This signal disables write access to some secure system control processor registers.
cpuporeset[4] 2.7.2 Signal protocol Slave Signal initializes all processor logic including NEON, VFP, Debug, PTM, breakpoint and watchpoint.
event 2.7.2 Signal protocol Peer This peer port of event input (and output) is for wakeup from WFE.
fiq[4] 2.7.2 Signal protocol Slave This signal drives the CPU's fast-interrupt handling.
fiqout[4] 2.7.2 Signal protocol Master This signal exports internal VGIC FIQ signal to the CPU..
irq[4] 2.7.2 Signal protocol Slave This signal drives the CPU's interrupt handling.
irqout[4] 2.7.2 Signal protocol Master This signal exports internal VGIC IRQ signal to the CPU.
irqs[480] 2.7.2 Signal protocol Slave These signals drive the CPU's interrupt controller interrupt lines.
l2reset 2.7.2 Signal protocol Slave This signal resets the shared L2 memory system, interrupt controller and timer logic.
periphbase 2.7.5 Value_64 protocol Slave This port sets the base address of the private peripheral region.
pmuirq[4] 2.7.2 Signal protocol Master Interrupt signal from performance monitoring unit.
presetdbg 2.7.2 Signal protocol Slave Signal initializes the shared Debug APB, CTI and CTM logic.
pvbus_m0 PVBus Master The core will generate bus requests on this port.
reset[4] 2.7.2 Signal protocol Slave Raising this signal will put the core into reset mode.
standbywfe[4] 2.7.2 Signal protocol Master This signal indicates if a core is in WFE state.
standbywfi[4] 2.7.2 Signal protocol Master This signal indicates if a core is in WFI state.
standbywfil2 2.7.2 Signal protocol Master Indicate that all the individual processors and the L2 memory system are in a WFI state.
teinit[4] 2.7.2 Signal protocol Slave This signal enables Thumb exceptions (controls the SCTLR.TE bit).
ticks[4] 2.6.3 InstructionCount protocol Master This port should be connected to one of the two ticks ports on a 'visualisation' component, in order to display a running instruction count.
vfiq[4] 2.7.2 Signal protocol Slave Virtual FIQ inputs. Note that the fiq pins are wired directly to the core if there is no internal VGIC. If there is an internal VGIC then these are ignored.
vinithi[4] 2.7.2 Signal protocol Slave This signal controls the location of the exception vectors at reset.
virq[4] 2.7.2 Signal protocol Slave Virtual IRQ inputs. Note that the irq pins are wired directly to the core if there is no internal VGIC. If there is an internal VGIC then these are ignored.
virtio_s PVBus Slave The virtio coherent port, hooks directly into the L2 system and becomes coherent (assuming attributes are set correctly).

Table 3-134 Parameters for Cluster_ARM_Cortex-A7

Name Type Default value Description
BROADCASTCACHEMAINT bool 0x1 Enable broadcasting of cache maintenance operations to downstream caches. The broadcastcachemaint signal will override this value if used.
BROADCASTINNER bool 0x1 Enable broadcasting of Inner Shareable transactions. The broadcastinner signal will override this value if used.
BROADCASTOUTER bool 0x1 Enable broadcasting of Outer Shareable transactions. The broadcastouter signal will override this value if used.
CFGSDISABLE bool 0x0 Disable some accesses to GIC registers
CLUSTER_ID int 0x0 Processor cluster ID value
PERIPHBASE int 0x13080000 Base address of peripheral memory space
cpi_div int 0x1 Divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 Multiplier for calculating CPI (Cycles Per Instruction)
dic-spi_count int 0x40 Number of shared peripheral interrupts implemented
disable_periph_decoder bool 0x0 Disable memory mapped access to gic system registers
internal_vgic bool 0x1 Configures whether the model of the processor contains a VGIC
l1_dcache-hit_latency int 0x0 L1 D-Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when l1_dcache-state_modelled=true.
l1_dcache-maintenance_latency int 0x0 L1 D-Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when l1_dcache-state_modelled=true.
l1_dcache-miss_latency int 0x0 L1 D-Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when l1_dcache-state_modelled=true.
l1_dcache-read_access_latency int 0x0 L1 D-Cache timing annotation latency for read accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l1_dcache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, this is only used when l1_dcache-state_modelled=true.
l1_dcache-read_latency int 0x0 L1 D-Cache timing annotation latency for read accesses given in ticks per byte accessed.l1_dcache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when l1_dcache-state_modelled=true.
l1_dcache-snoop_data_transfer_latency int 0x0 L1 D-Cache timing annotation latency for received snoop accesses that perform a data transfer given in ticks per byte accessed. This is only used when l1_dcache-state_modelled=true.
l1_dcache-state_modelled bool 0x0 Set whether L1 D-cache has stateful implementation
l1_dcache-write_access_latency int 0x0 L1 D-Cache timing annotation latency for write accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l1_dcache-write_latency is set. This is only used when l1_dcache-state_modelled=true.
l1_dcache-write_latency int 0x0 L1 D-Cache timing annotation latency for write accesses given in ticks per byte accessed. l1_dcache-write_access_latency must be set to 0 for per-byte latencies to be applied. This is only used when l1_dcache-state_modelled=true.
l1_icache-hit_latency int 0x0 L1 I-Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when l1_icache-state_modelled=true.
l1_icache-maintenance_latency int 0x0 L1 I-Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when l1_icache-state_modelled=true.
l1_icache-miss_latency int 0x0 L1 I-Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when l1_icache-state_modelled=true.
l1_icache-read_access_latency int 0x0 L1 I-Cache timing annotation latency for read accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l1_icache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, this is only used when l1_icache-state_modelled=true.
l1_icache-read_latency int 0x0 L1 I-Cache timing annotation latency for read accesses given in ticks per byte accessed.l1_icache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when l1_icache-state_modelled=true.
l1_icache-state_modelled bool 0x0 Set whether L1 I-cache has stateful implementation
l2_cache-hit_latency int 0x0 L2 Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when l2_cache-state_modelled=true.
l2_cache-maintenance_latency int 0x0 L2 Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when l2_cache-state_modelled=true.
l2_cache-miss_latency int 0x0 L2 Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when l2_cache-state_modelled=true.
l2_cache-read_access_latency int 0x0 L2 Cache timing annotation latency for read accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l2_cache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, this is only used when l2_cache-state_modelled=true.
l2_cache-read_latency int 0x0 L2 Cache timing annotation latency for read accesses given in ticks per byte accessed.l2_cache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when l2_cache-state_modelled=true.
l2_cache-size int 0x80000 Set L2 cache size in bytes
l2_cache-snoop_data_transfer_latency int 0x0 L2 Cache timing annotation latency for received snoop accesses that perform a data transfer given in ticks per byte accessed. This is only used when l2_cache-state_modelled=true.
l2_cache-snoop_issue_latency int 0x0 L2 Cache timing annotation latency for snoop accesses issued by this cache in total ticks. This is only used when l2_cache-state_modelled=true.
l2_cache-state_modelled bool 0x0 Set whether L2 cache has stateful implementation
l2_cache-write_access_latency int 0x0 L2 Cache timing annotation latency for write accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l2_cache-write_latency is set. This is only used when l2_cache-state_modelled=true.
l2_cache-write_latency int 0x0 L2 Cache timing annotation latency for write accesses given in ticks per byte accessed. l2_cache-write_access_latency must be set to 0 for per-byte latencies to be applied. This is only used when l2_cache-state_modelled=true.

Table 3-135 Parameters for ARM_Cortex-A7

Name Type Default value Description
cpu0.CFGEND bool 0x0 Initialize to BE8 endianness
cpu0.CP15SDISABLE bool 0x0 Initialize to disable access to some CP15 registers
cpu0.DBGROMADDR int 0x12000003 This value is used to initialize the CP15 DBGDRAR register. Bits[39:12] of this register specify the ROM table physical address
cpu0.DBGROMADDRV bool 0x1 If true this sets bits[1:0] of the CP15 DBGDRAR to indicate that the address is valid
cpu0.DBGSELFADDR int 0x10003 This value is used to initialize the CP15 DBGDSAR register. Bits[39:17] of this register specify the ROM table physical address
cpu0.DBGSELFADDRV bool 0x1 If true this sets bits[1:0] of the CP15 DBGDSAR to indicate that the address is valid
cpu0.TEINIT bool 0x0 T32 exception enable. The default has exceptions including reset handled in A32 state
cpu0.VINITHI bool 0x0 Initialize with high vectors enabled
cpu0.ase-present bool 0x1 Set whether CT model has been built with NEON support
cpu0.l1_dcache-size int 0x8000 Size of L1 D-cache
cpu0.l1_icache-size int 0x8000 Size of L1 I-cache
cpu0.min_sync_level int 0x0 Force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
cpu0.semihosting-ARM_HLT int 0xf000 ARM HLT number for semihosting
cpu0.semihosting-ARM_SVC int 0x123456 ARM SVC number for semihosting
cpu0.semihosting-Thumb_HLT int 0x3c Thumb HLT number for semihosting
cpu0.semihosting-Thumb_SVC int 0xab Thumb SVC number for semihosting
cpu0.semihosting-cmd_line string "" Command line available to semihosting SVC calls
cpu0.semihosting-cwd string "" Base directory for semihosting file access.
cpu0.semihosting-enable bool 0x1 Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false
cpu0.semihosting-heap_base int 0x0 Virtual address of heap base
cpu0.semihosting-heap_limit int 0xf000000 Virtual address of top of heap
cpu0.semihosting-hlt-enable bool 0x0 Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true
cpu0.semihosting-stack_base int 0x10000000 Virtual address of base of descending stack
cpu0.semihosting-stack_limit int 0xf000000 Virtual address of stack limit
cpu0.vfp-enable_at_reset bool 0x0 Enable coprocessor access and VFP at reset
cpu0.vfp-present bool 0x1 Set whether CT model has been built with VFP support
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