1.4.5 TLBs in PV models

The PV models implement Translation Lookaside Buffers (TLBs) and model most aspects of TLB behavior.

Note:

If the device-accurate-tlb parameter is set to false, the simulation uses a different number of TLBs if this improves simulation performance. The simulation is architecturally accurate, but not device accurate. Architectural accuracy is almost always sufficient. Set device-accurate-tlb parameter to true if you require device accuracy.

These TLB registers do not have working implementations:

  • Primary memory remap register.
  • Normal memory remap register.

In addition, the simulation does not distinguish peripheral accesses from data accesses, so it ignores configuration of the peripheral port memory remap register.

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