1.4.7 Timing in PV models

Programmer’s View (PV) models are loosely timed.

  • Caches and write buffers are not modeled, so all memory access timing is effectively zero wait state.
  • All instructions execute, in aggregate, in one cycle of the component master clock input.
  • Interrupts are not taken at every instruction boundary.
  • Some sequences of instructions are executed atomically, ahead of the master clock of a component, so that system time does not advance during execution. This difference in behavior can affect sequential access of device registers, where devices are expecting time to move on between accesses.
  • DMA to and from Tightly Coupled Memory (TCM) is atomic.
Non-ConfidentialPDF file icon PDF version100964_1161_00_en
Copyright © 2014–2019 Arm Limited or its affiliates. All rights reserved.