2.1.2 AMBAPV protocol

The AMBAPV protocol defines behaviors for single read and single write transactions. This covers ARM® AMBA® AXI4, AXI3, AHB and APB bus protocol families, at the PV level.

In addition, the AMBAPV protocol provides support for AMBA protocol additional control information:

  • Protection units.
  • Exclusive access and locked access mechanisms.
  • System-level caches.

The behaviors of the protocol are:

read()

Completes a single read transaction at the given address for the given size in bytes. Additional AMBA protocol control information can be specified using the ctrl parameter. The socket_id parameter must be set to 0 in this context.

read(int socket_id, const sc_dt::uint64 &addr,
    unsigned char *data, unsigned int size,
    const amba_pv::amba_pv_control *ctrl,
    sc_core::sc_time &t):
    amba_pv::amba_pv_resp_t
write()

Completes a single write transaction at the given address with specified data and write strobes. The size of the data is specified in bytes. Additional AMBA protocol control information can be specified using the ctrl parameter. The socket_id parameter must be set to 0 in this context.

write(int socket_id, const sc_dt::uint64 &addr,
    unsigned char *data, unsigned int size,
    const amba_pv::amba_pv_control *ctrl,
    unsigned char *strb, sc_core::sc_time &t): 
    amba_pv::amba_pv_resp_t
debug_read()

Completes a debug read transaction from a given address without causing any side effects. Specify the number of bytes to read in the length parameter. The number of successfully read values is returned. Additional AMBA protocol control information can be specified in the ctrl parameter. The socket_id parameter must be set to 0 in this context. This behavior is empty by default and returns 0.

debug_read(int socket_id, const sc_dt::uint64 &addr,
    unsigned char *data, unsigned int length,
    const amba_pv::amba_pv_control *ctrl): 
    unsigned int
debug_write()

Completes a debug write transaction to a given address without causing any side effects. Specify the number of bytes to write in the length parameter. The number of successfully written values is returned. Additional AMBA protocol control information can be specified in the ctrl parameter. The socket_id parameter must be set to 0 in this context. This behavior is empty by default and returns 0.

debug_write(int socket_id, const sc_dt::uint64 &addr,
    unsigned char *data, unsigned int length,
    const amba_pv::amba_pv_control *ctrl): 
    unsigned int
b_transport()

This is an optional slave behavior for blocking transport. It completes a single transaction using the blocking transport interface. The amba_pv::amba_pv_extension must be added to the transaction before calling this behavior. The socket_id parameter must be set to 0 in this context.

b_transport(int socket_id,
    amba_pv::amba_pv_transaction &trans, sc_core::sctime &t)
transport_dbg()

This optional slave behavior implements the TLM debug transport interface. An amba_pv::amba_pv_extension object must be added to the transaction before calling this behavior. The socket_id parameter must be set to 0 in this context.

transport_dbg(int socket_id, amba_pv::amba_pv_transaction &trans, sc_core::sctime &t): unsigned int
get_direct_mem_ptr()

This is an optional slave behavior for requesting a DMI access to a given address. It returns a reference to a DMI descriptor that contains the bounds of the granted DMI region. Returns true if a DMI region is granted, false otherwise.

The amba_pv::amba_pv_extension must be added to the transaction before calling this behavior. The socket_id parameter must be set to 0 in this context.

get_direct_mem_ptr(int socket_id,
    amba_pv::amba_pv_transaction &trans,
    tlm::tlm_dmi &dmi_data):
    bool
invalidate_direct_mem_ptr()

This is an optional master behavior to invalidate a DMI request. It invalidates DMI pointers that were previously established for the given DMI region. The socket_id parameter is 0 in this context.

invalidate_direct_mem_ptr(int socket_id,
    sc_dt::uint64 start_range, sc_dt::uint64 end_range)

The generic payload data is formatted as an array of bytes in order of ascending bus address. This means that irrespective of the host machine endianness or modeled bus width, a little endian master must write the bytes of a word in increasing significance as the array index increases and a big endian master must write the bytes of a word in decreasing significance as the array index increases. A master or slave whose endianness does not match the endianness of the host machine must endian swap any access to the payload data that is wider than one byte. The same byte ordering rule applies to memory accesses using DMI pointers.

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