8.4 MPS2 - interrupt assignments

This section describes the interrupt assignments.

Table 8-3 Interrupt assignments

Number Interrupt
NMI Watchdog.
0 UART 0 receive interrupt.
1 UART 0 transmit interrupt.
2 UART 1 receive interrupt.
3 UART 1 transmit interrupt.
4 UART 2 receive interrupt.
5 UART 2 transmit interrupt.
6 GPIO 0, 2 combined interrupt.
7 GPIO 1, 3 combined interrupt.
8 Timer 0.
9 Timer 1.
10 Dual Timer.
11 SPI #1 (LCD). The LCD had shared SPI #0 and SPI #1.
12 UART overflow (0, 1, 2).
13 Ethernet.
14 Audio I2S.
15 Touch screen.
16-31 GPIO 0 individual interrupts.
32-47 GPIO 1 individual interrupts. Armv8‑M additions.
48 SPI #0. Armv8‑M addition.
49 Reserved.
50 TRNG (Secure). Armv8‑M addition.
51 Unique ID and Secure storage (Secure). Armv8‑M addition.
52 DMA controller #0.
53 DMA controller #1.
54 SecureErrorIRQ. Armv8‑M addition.a
a Detection of Non-secure access to Secure address spaces (including other bus masters). Generated by Memory Gating unit, Peripheral Gating units, bus gasket for legacy bus masters.
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