3.4.3 ARMAEMv8MCT

ARMAEMv8MCT CPU component. This model is written in C++.

ARMAEMv8MCT contains the following CADI targets:

  • ARM_AEMv8M

ARMAEMv8MCT contains the following MTI components:

Table 3-76 Ports

Name Protocol Type Description
ahbd PVBus Slave Debug AHB - core bus slave driven by the DAP.
ahbp_m PVBus Master The core will generate Vendor System data accesses on this port.
ahbs PVBus Slave External master (e.g. DMA) can write TCMs (whether or not enabled in xTCMCR).
auxfault 2.7.4 Value protocol Slave This is wired to the Auxiliary Fault Status Register.
bigend 2.7.2 Signal protocol Slave Configure big endian data format.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
cpuwait 2.7.2 Signal protocol Slave When this signal is HIGH out of reset, it forces the processor into a quiescent state that delays its boot-up sequence and instruction execution until this signal is driven LOW.
currpri 2.7.4 Value protocol Master Current execution priority.
dap_s PVBus Slave Debug Access Port (DAP).
dbgen 2.7.2 Signal protocol Slave Invasive debug enable.
dbgrestart 2.7.2 Signal protocol Slave External debug request.
dbgrestarted 2.7.2 Signal protocol Master External debug request.
edbgrq 2.7.2 Signal protocol Slave External debug request.
etm_reset 2.7.2 Signal protocol Slave Separate reset for ETM, if param "has_etm_reset" is true.
event 2.7.2 Signal protocol Peer This peer port of event input (and output) is for wakeup from WFE and corresponds to the RTL TXEV and RXEV signals.
fpxxc 2.7.4 Value protocol Master Port which sends the value of the FPXXC cumulative exception flags.
halted 2.7.2 Signal protocol Master External debug request.
idau PVBus Master The core will generate IDAU Bus request.
idau_invalidate_region 2.7.5 Value_64 protocol Slave 64 bit number to invalid IDAU memory ranage (start_address<<32|end_address)
initpahben 2.7.2 Signal protocol Slave Enable P-AHB on the next reset
initvtor_ns 2.7.4 Value protocol Slave Reset configuration port - Non-Secure Vector table offset (VTOR.TBLOFF[31:7]) out of reset This port remains functional no matter ARMv8-M Security Extensions are included or not When ARMv8-M Security Extensions are not included, all exceptions will use NS vector base address given by this port.
initvtor_s 2.7.4 Value protocol Slave Reset configuration port - Secure Vector table offset (VTOR.TBLOFF[31:7]) out of reset It becomes functional when ARMv8-M Security Extensions are included When ARMv8-M Security Extensions are not included, this port will be ignored.
intisr[496] 2.7.2 Signal protocol Slave This signal array delivers signals to the NVIC.
intnmi 2.7.2 Signal protocol Slave Configure non maskable interrupt.
intnum 2.7.4 Value protocol Master Exception number of the current execution context (from IPSR[8:0]) When the processor is in Thread mode, INTNUM is 0 When the processor is in Handler mode, INTNUM is the exception number of the currently-executing exception.
io_port_in PVBus Slave I/O port pair. See the documentation for the io_port_out port.
io_port_out PVBus Master I/O port pair. Used if IOP is true. Transactions from io_port_out which do not "match" should be returned via io_port_in. For performance reasons, the I/O port interface is not modelled directly. Instead, a simple PVBus gasket is inserted at the point in the memory system where the I/O port would be. In hardware, a device would be attached to the port which would tell the CPU whether it would like to intercept each transaction, given its address. This can be modelled in a performant manner by connecting a PVBusMapper-based device to io_port_out which intercepts transactions of interest and passes other transactions back to the CPU via io_port_in. Your I/O port device model is also responsible for aborting transactions which would be aborted on hardware (e.g. exclusives) if necessary.
locknsmpu 2.7.2 Signal protocol Slave Disable writes to the Non-Secure MPU_*_NS registers
locknsvtor 2.7.2 Signal protocol Slave Disable writes to VTOR_NS
lockpahb 2.7.2 Signal protocol Slave P-AHB related ports Disable writes to PAHBCR
locksau 2.7.2 Signal protocol Slave Disable writes to the SAU_* registers
locksmpu 2.7.2 Signal protocol Slave Disable writes to the Secure MPU_* registers
locksvtaircr 2.7.2 Signal protocol Slave Disable writes to VTOR_S, AIRCR.PRIS, AIRCR.BFHFNMINS
lockup 2.7.2 Signal protocol Master Asserted when the processor is in lockup state.
niden 2.7.2 Signal protocol Slave Non-invasive debug enable.
poreset 2.7.2 Signal protocol Slave Raising this signal will do a power-on reset of the core.
pv_ppbus_m PVBus Master The core will generate External Private Peripheral Bus requests on this port.
pvbus_m PVBus Master The core will generate bus requests on this port.
sleepdeep 2.7.2 Signal protocol Master Asserted when the processor is in deep sleep.
sleeping 2.7.2 Signal protocol Master Asserted when the processor is in sleep.
spiden 2.7.2 Signal protocol Slave Secure invasive debug enable.
spniden 2.7.2 Signal protocol Slave Secure non-invasive debug enable.
stcalib[2] 2.7.4 Value protocol Slave This is the calibration value for the SysTick timer.
stclk ClockSignal Slave This is the reference clock for the SysTick timer.
sysreset 2.7.2 Signal protocol Slave Raising this signal will put the core into reset mode (but does not reset the debug logic).
sysresetreq 2.7.2 Signal protocol Master Asserted to indicate that a reset is required.
ticks 2.6.3 InstructionCount protocol Master Port allowing the number of instructions since startup to be read from the CPU.

Table 3-77 Parameters for ARM_AEMv8M

Name Type Default value Description
AIRCR.ENDIANNESS bool 0x0 Initialize processor to big endian mode
BB_PRESENT bool 0x0 Enable bitbanding
CFGMEMALIAS int 0x0 Memory address alias bit for the ITCM, DTCM and P-AHB regions. 0=No alias, 1=Alias bit 24, 2=Alias bit 25, 4=Alias bit 26, 8=Alias bit 27, 16=Alias bit 28
CFGPAHBSZ int 0x0 Size of the P-AHB peripheral port memory region. 0=P-AHB disabled, 1=64MB, 2=128MB, 3=256MB, 4=512MB
DTGU bool 0x0 DTCM Security Gate Unit included
DTGUBLKSZ int 0x3 DTCM gate unit block size. Size=pow(2, DTGUBLKSZ + 5) bytes
DTGUMAXBLKS int 0x0 Maxiumum number of DTCM gate unit blocks. Number of blocks=pow(2, DTGUMAXBLKS)
DWT_CTRL.NOCYCCNT bool 0x0 DWT cycle-counter not present (v8M_bl/v6M never have one).
DWT_CTRL.NOPRFCNT bool 0x0 DWT performance-counters not present (v8M_bl/v6M never have them).
DWT_CTRL.NUMCOMP int 0x4 Number of watchpoint unit comparators implemented
DWT_DEVARCH.REVISION int 0x1 0: V2, 1: V2.1.
DWT_FUNCTION0.ID int 0xb Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION0. If 'baseline' is set, invalid ID bits are cleared
DWT_FUNCTION1.ID int 0x1e Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION1. If 'baseline' is set, invalid ID bits are cleared
DWT_FUNCTION10.ID int 0xb Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION10. If 'baseline' is set, invalid ID bits are cleared
DWT_FUNCTION11.ID int 0x1e Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION11. If 'baseline' is set, invalid ID bits are cleared
DWT_FUNCTION12.ID int 0xb Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION12. If 'baseline' is set, invalid ID bits are cleared
DWT_FUNCTION13.ID int 0x1e Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION13. If 'baseline' is set, invalid ID bits are cleared
DWT_FUNCTION14.ID int 0xb Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION14. If 'baseline' is set, invalid ID bits are cleared
DWT_FUNCTION15.ID int 0x1e Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION15. If 'baseline' is set, invalid ID bits are cleared
DWT_FUNCTION2.ID int 0xb Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION2. If 'baseline' is set, invalid ID bits are cleared
DWT_FUNCTION3.ID int 0x1e Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION3. If 'baseline' is set, invalid ID bits are cleared
DWT_FUNCTION4.ID int 0xb Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION4. If 'baseline' is set, invalid ID bits are cleared
DWT_FUNCTION5.ID int 0x1e Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION5. If 'baseline' is set, invalid ID bits are cleared
DWT_FUNCTION6.ID int 0xb Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION6. If 'baseline' is set, invalid ID bits are cleared
DWT_FUNCTION7.ID int 0x1e Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION7. If 'baseline' is set, invalid ID bits are cleared
DWT_FUNCTION8.ID int 0xb Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION8. If 'baseline' is set, invalid ID bits are cleared
DWT_FUNCTION9.ID int 0x1e Sets the capabilities of the comparator that is accessible via the register, DWT_FUNCTION9. If 'baseline' is set, invalid ID bits are cleared
DWT_TRACE bool 0x1 Support for DWT trace, controls the DWT_CTRL.NOTRCPKT bit. false : No DWT trace included, true: DWT trace included
FP_CTRL.NUM_CODE int 0x8 Number of breakpoint unit comparators implemented (limited to 15 in V6M or baseline)
FP_CTRL.NUM_LIT int 0x0 How many Literals FPB supports remapping (ignored if baseline or TZM)
FP_REMAP.RMPSPT bool 0x1 FPB supports remapping (ignored if baseline or SECEXT)
ID_DFR0.Debug_Model_M_profile bool 0x1 Set whether debug extensions are implemented
INITVTOR_NS int 0x0 Non-Secure vector-table offset at reset
INITVTOR_S int 0x0 Secure vector-table offset at reset
ITGU bool 0x0 ITCM Security Gate Unit included
ITGUBLKSZ int 0x3 ITCM gate unit block size. Size=pow(2, ITGUBLKSZ + 5) bytes
ITGUMAXBLKS int 0x0 Maxiumum number of ITCM gate unit blocks. Number of blocks=pow(2, ITGUMAXBLKS)
ITM bool 0x1 Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included (unless baseline)
ITM_HAS_LSR bool 0x1 ITM support LAR and LSR for software lock
LVL_WIDTH int 0x3 Number of bits of interrupt priority (baseline has 2)
MPU_TYPE_NS.DREGION int 0x10 Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions
MPU_TYPE_S.DREGION int 0x10 Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored
MVFR0.Double-precision bool 0x1 Support 8-byte floats
NUM_IRQ int 0x10 Number of user interrupts
REGISTER_POP_ORDER string "R0-R3,R12,R14,RETURN_ADDR,CPSR,S0-S15,FPSCR,PADDING,S16-S31" Order in which the registers are popped off the stack during exception return. A comma separated list of register names and ranges.
REGISTER_PUSH_ORDER string "R0-R3,R12,R14,RETURN_ADDR,CPSR,S0-S15,FPSCR,PADDING,S16-S31" Order in which the registers are pushed on to the stack during exception handling. A comma separated list of register names and ranges.
SAU_CTRL.ALLNS bool 0x0 At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set
SAU_CTRL.ENABLE bool 0x0 Enable SAU at reset
SAU_REGION0.BADDR int 0x0 Base address of SAU region0 at reset
SAU_REGION0.ENABLE bool 0x0 Enable SAU region0 at reset
SAU_REGION0.LADDR int 0x0 Limit address of SAU region0 at reset
SAU_REGION0.NSC bool 0x0 Set NSC for SAU region0 at reset
SAU_REGION1.BADDR int 0x0 Base address of SAU region1 at reset
SAU_REGION1.ENABLE bool 0x0 Enable SAU region1 at reset
SAU_REGION1.LADDR int 0x0 Limit address of SAU region1 at reset
SAU_REGION1.NSC bool 0x0 Set NSC for SAU region1 at reset
SAU_REGION10.BADDR int 0x0 Base address of SAU region10 at reset
SAU_REGION10.ENABLE bool 0x0 Enable SAU region10 at reset
SAU_REGION10.LADDR int 0x0 Limit address of SAU region10 at reset
SAU_REGION10.NSC bool 0x0 Set NSC for SAU region10 at reset
SAU_REGION11.BADDR int 0x0 Base address of SAU region11 at reset
SAU_REGION11.ENABLE bool 0x0 Enable SAU region11 at reset
SAU_REGION11.LADDR int 0x0 Limit address of SAU region11 at reset
SAU_REGION11.NSC bool 0x0 Set NSC for SAU region11 at reset
SAU_REGION12.BADDR int 0x0 Base address of SAU region12 at reset
SAU_REGION12.ENABLE bool 0x0 Enable SAU region12 at reset
SAU_REGION12.LADDR int 0x0 Limit address of SAU region12 at reset
SAU_REGION12.NSC bool 0x0 Set NSC for SAU region12 at reset
SAU_REGION13.BADDR int 0x0 Base address of SAU region13 at reset
SAU_REGION13.ENABLE bool 0x0 Enable SAU region13 at reset
SAU_REGION13.LADDR int 0x0 Limit address of SAU region13 at reset
SAU_REGION13.NSC bool 0x0 Set NSC for SAU region13 at reset
SAU_REGION14.BADDR int 0x0 Base address of SAU region14 at reset
SAU_REGION14.ENABLE bool 0x0 Enable SAU region14 at reset
SAU_REGION14.LADDR int 0x0 Limit address of SAU region14 at reset
SAU_REGION14.NSC bool 0x0 Set NSC for SAU region14 at reset
SAU_REGION15.BADDR int 0x0 Base address of SAU region15 at reset
SAU_REGION15.ENABLE bool 0x0 Enable SAU region15 at reset
SAU_REGION15.LADDR int 0x0 Limit address of SAU region15 at reset
SAU_REGION15.NSC bool 0x0 Set NSC for SAU region15 at reset
SAU_REGION16.BADDR int 0x0 Base address of SAU region16 at reset
SAU_REGION16.ENABLE bool 0x0 Enable SAU region16 at reset
SAU_REGION16.LADDR int 0x0 Limit address of SAU region16 at reset
SAU_REGION16.NSC bool 0x0 Set NSC for SAU region16 at reset
SAU_REGION17.BADDR int 0x0 Base address of SAU region17 at reset
SAU_REGION17.ENABLE bool 0x0 Enable SAU region17 at reset
SAU_REGION17.LADDR int 0x0 Limit address of SAU region17 at reset
SAU_REGION17.NSC bool 0x0 Set NSC for SAU region17 at reset
SAU_REGION18.BADDR int 0x0 Base address of SAU region18 at reset
SAU_REGION18.ENABLE bool 0x0 Enable SAU region18 at reset
SAU_REGION18.LADDR int 0x0 Limit address of SAU region18 at reset
SAU_REGION18.NSC bool 0x0 Set NSC for SAU region18 at reset
SAU_REGION19.BADDR int 0x0 Base address of SAU region19 at reset
SAU_REGION19.ENABLE bool 0x0 Enable SAU region19 at reset
SAU_REGION19.LADDR int 0x0 Limit address of SAU region19 at reset
SAU_REGION19.NSC bool 0x0 Set NSC for SAU region19 at reset
SAU_REGION2.BADDR int 0x0 Base address of SAU region2 at reset
SAU_REGION2.ENABLE bool 0x0 Enable SAU region2 at reset
SAU_REGION2.LADDR int 0x0 Limit address of SAU region2 at reset
SAU_REGION2.NSC bool 0x0 Set NSC for SAU region2 at reset
SAU_REGION20.BADDR int 0x0 Base address of SAU region20 at reset
SAU_REGION20.ENABLE bool 0x0 Enable SAU region20 at reset
SAU_REGION20.LADDR int 0x0 Limit address of SAU region20 at reset
SAU_REGION20.NSC bool 0x0 Set NSC for SAU region20 at reset
SAU_REGION21.BADDR int 0x0 Base address of SAU region21 at reset
SAU_REGION21.ENABLE bool 0x0 Enable SAU region21 at reset
SAU_REGION21.LADDR int 0x0 Limit address of SAU region21 at reset
SAU_REGION21.NSC bool 0x0 Set NSC for SAU region21 at reset
SAU_REGION22.BADDR int 0x0 Base address of SAU region22 at reset
SAU_REGION22.ENABLE bool 0x0 Enable SAU region22 at reset
SAU_REGION22.LADDR int 0x0 Limit address of SAU region22 at reset
SAU_REGION22.NSC bool 0x0 Set NSC for SAU region22 at reset
SAU_REGION23.BADDR int 0x0 Base address of SAU region23 at reset
SAU_REGION23.ENABLE bool 0x0 Enable SAU region23 at reset
SAU_REGION23.LADDR int 0x0 Limit address of SAU region23 at reset
SAU_REGION23.NSC bool 0x0 Set NSC for SAU region23 at reset
SAU_REGION24.BADDR int 0x0 Base address of SAU region24 at reset
SAU_REGION24.ENABLE bool 0x0 Enable SAU region24 at reset
SAU_REGION24.LADDR int 0x0 Limit address of SAU region24 at reset
SAU_REGION24.NSC bool 0x0 Set NSC for SAU region24 at reset
SAU_REGION25.BADDR int 0x0 Base address of SAU region25 at reset
SAU_REGION25.ENABLE bool 0x0 Enable SAU region25 at reset
SAU_REGION25.LADDR int 0x0 Limit address of SAU region25 at reset
SAU_REGION25.NSC bool 0x0 Set NSC for SAU region25 at reset
SAU_REGION26.BADDR int 0x0 Base address of SAU region26 at reset
SAU_REGION26.ENABLE bool 0x0 Enable SAU region26 at reset
SAU_REGION26.LADDR int 0x0 Limit address of SAU region26 at reset
SAU_REGION26.NSC bool 0x0 Set NSC for SAU region26 at reset
SAU_REGION27.BADDR int 0x0 Base address of SAU region27 at reset
SAU_REGION27.ENABLE bool 0x0 Enable SAU region27 at reset
SAU_REGION27.LADDR int 0x0 Limit address of SAU region27 at reset
SAU_REGION27.NSC bool 0x0 Set NSC for SAU region27 at reset
SAU_REGION28.BADDR int 0x0 Base address of SAU region28 at reset
SAU_REGION28.ENABLE bool 0x0 Enable SAU region28 at reset
SAU_REGION28.LADDR int 0x0 Limit address of SAU region28 at reset
SAU_REGION28.NSC bool 0x0 Set NSC for SAU region28 at reset
SAU_REGION29.BADDR int 0x0 Base address of SAU region29 at reset
SAU_REGION29.ENABLE bool 0x0 Enable SAU region29 at reset
SAU_REGION29.LADDR int 0x0 Limit address of SAU region29 at reset
SAU_REGION29.NSC bool 0x0 Set NSC for SAU region29 at reset
SAU_REGION3.BADDR int 0x0 Base address of SAU region3 at reset
SAU_REGION3.ENABLE bool 0x0 Enable SAU region3 at reset
SAU_REGION3.LADDR int 0x0 Limit address of SAU region3 at reset
SAU_REGION3.NSC bool 0x0 Set NSC for SAU region3 at reset
SAU_REGION30.BADDR int 0x0 Base address of SAU region30 at reset
SAU_REGION30.ENABLE bool 0x0 Enable SAU region30 at reset
SAU_REGION30.LADDR int 0x0 Limit address of SAU region30 at reset
SAU_REGION30.NSC bool 0x0 Set NSC for SAU region30 at reset
SAU_REGION31.BADDR int 0x0 Base address of SAU region31 at reset
SAU_REGION31.ENABLE bool 0x0 Enable SAU region31 at reset
SAU_REGION31.LADDR int 0x0 Limit address of SAU region31 at reset
SAU_REGION31.NSC bool 0x0 Set NSC for SAU region31 at reset
SAU_REGION32.BADDR int 0x0 Base address of SAU region32 at reset
SAU_REGION32.ENABLE bool 0x0 Enable SAU region32 at reset
SAU_REGION32.LADDR int 0x0 Limit address of SAU region32 at reset
SAU_REGION32.NSC bool 0x0 Set NSC for SAU region32 at reset
SAU_REGION33.BADDR int 0x0 Base address of SAU region33 at reset
SAU_REGION33.ENABLE bool 0x0 Enable SAU region33 at reset
SAU_REGION33.LADDR int 0x0 Limit address of SAU region33 at reset
SAU_REGION33.NSC bool 0x0 Set NSC for SAU region33 at reset
SAU_REGION34.BADDR int 0x0 Base address of SAU region34 at reset
SAU_REGION34.ENABLE bool 0x0 Enable SAU region34 at reset
SAU_REGION34.LADDR int 0x0 Limit address of SAU region34 at reset
SAU_REGION34.NSC bool 0x0 Set NSC for SAU region34 at reset
SAU_REGION35.BADDR int 0x0 Base address of SAU region35 at reset
SAU_REGION35.ENABLE bool 0x0 Enable SAU region35 at reset
SAU_REGION35.LADDR int 0x0 Limit address of SAU region35 at reset
SAU_REGION35.NSC bool 0x0 Set NSC for SAU region35 at reset
SAU_REGION36.BADDR int 0x0 Base address of SAU region36 at reset
SAU_REGION36.ENABLE bool 0x0 Enable SAU region36 at reset
SAU_REGION36.LADDR int 0x0 Limit address of SAU region36 at reset
SAU_REGION36.NSC bool 0x0 Set NSC for SAU region36 at reset
SAU_REGION37.BADDR int 0x0 Base address of SAU region37 at reset
SAU_REGION37.ENABLE bool 0x0 Enable SAU region37 at reset
SAU_REGION37.LADDR int 0x0 Limit address of SAU region37 at reset
SAU_REGION37.NSC bool 0x0 Set NSC for SAU region37 at reset
SAU_REGION38.BADDR int 0x0 Base address of SAU region38 at reset
SAU_REGION38.ENABLE bool 0x0 Enable SAU region38 at reset
SAU_REGION38.LADDR int 0x0 Limit address of SAU region38 at reset
SAU_REGION38.NSC bool 0x0 Set NSC for SAU region38 at reset
SAU_REGION39.BADDR int 0x0 Base address of SAU region39 at reset
SAU_REGION39.ENABLE bool 0x0 Enable SAU region39 at reset
SAU_REGION39.LADDR int 0x0 Limit address of SAU region39 at reset
SAU_REGION39.NSC bool 0x0 Set NSC for SAU region39 at reset
SAU_REGION4.BADDR int 0x0 Base address of SAU region4 at reset
SAU_REGION4.ENABLE bool 0x0 Enable SAU region4 at reset
SAU_REGION4.LADDR int 0x0 Limit address of SAU region4 at reset
SAU_REGION4.NSC bool 0x0 Set NSC for SAU region4 at reset
SAU_REGION40.BADDR int 0x0 Base address of SAU region40 at reset
SAU_REGION40.ENABLE bool 0x0 Enable SAU region40 at reset
SAU_REGION40.LADDR int 0x0 Limit address of SAU region40 at reset
SAU_REGION40.NSC bool 0x0 Set NSC for SAU region40 at reset
SAU_REGION41.BADDR int 0x0 Base address of SAU region41 at reset
SAU_REGION41.ENABLE bool 0x0 Enable SAU region41 at reset
SAU_REGION41.LADDR int 0x0 Limit address of SAU region41 at reset
SAU_REGION41.NSC bool 0x0 Set NSC for SAU region41 at reset
SAU_REGION42.BADDR int 0x0 Base address of SAU region42 at reset
SAU_REGION42.ENABLE bool 0x0 Enable SAU region42 at reset
SAU_REGION42.LADDR int 0x0 Limit address of SAU region42 at reset
SAU_REGION42.NSC bool 0x0 Set NSC for SAU region42 at reset
SAU_REGION43.BADDR int 0x0 Base address of SAU region43 at reset
SAU_REGION43.ENABLE bool 0x0 Enable SAU region43 at reset
SAU_REGION43.LADDR int 0x0 Limit address of SAU region43 at reset
SAU_REGION43.NSC bool 0x0 Set NSC for SAU region43 at reset
SAU_REGION44.BADDR int 0x0 Base address of SAU region44 at reset
SAU_REGION44.ENABLE bool 0x0 Enable SAU region44 at reset
SAU_REGION44.LADDR int 0x0 Limit address of SAU region44 at reset
SAU_REGION44.NSC bool 0x0 Set NSC for SAU region44 at reset
SAU_REGION45.BADDR int 0x0 Base address of SAU region45 at reset
SAU_REGION45.ENABLE bool 0x0 Enable SAU region45 at reset
SAU_REGION45.LADDR int 0x0 Limit address of SAU region45 at reset
SAU_REGION45.NSC bool 0x0 Set NSC for SAU region45 at reset
SAU_REGION46.BADDR int 0x0 Base address of SAU region46 at reset
SAU_REGION46.ENABLE bool 0x0 Enable SAU region46 at reset
SAU_REGION46.LADDR int 0x0 Limit address of SAU region46 at reset
SAU_REGION46.NSC bool 0x0 Set NSC for SAU region46 at reset
SAU_REGION47.BADDR int 0x0 Base address of SAU region47 at reset
SAU_REGION47.ENABLE bool 0x0 Enable SAU region47 at reset
SAU_REGION47.LADDR int 0x0 Limit address of SAU region47 at reset
SAU_REGION47.NSC bool 0x0 Set NSC for SAU region47 at reset
SAU_REGION48.BADDR int 0x0 Base address of SAU region48 at reset
SAU_REGION48.ENABLE bool 0x0 Enable SAU region48 at reset
SAU_REGION48.LADDR int 0x0 Limit address of SAU region48 at reset
SAU_REGION48.NSC bool 0x0 Set NSC for SAU region48 at reset
SAU_REGION49.BADDR int 0x0 Base address of SAU region49 at reset
SAU_REGION49.ENABLE bool 0x0 Enable SAU region49 at reset
SAU_REGION49.LADDR int 0x0 Limit address of SAU region49 at reset
SAU_REGION49.NSC bool 0x0 Set NSC for SAU region49 at reset
SAU_REGION5.BADDR int 0x0 Base address of SAU region5 at reset
SAU_REGION5.ENABLE bool 0x0 Enable SAU region5 at reset
SAU_REGION5.LADDR int 0x0 Limit address of SAU region5 at reset
SAU_REGION5.NSC bool 0x0 Set NSC for SAU region5 at reset
SAU_REGION50.BADDR int 0x0 Base address of SAU region50 at reset
SAU_REGION50.ENABLE bool 0x0 Enable SAU region50 at reset
SAU_REGION50.LADDR int 0x0 Limit address of SAU region50 at reset
SAU_REGION50.NSC bool 0x0 Set NSC for SAU region50 at reset
SAU_REGION51.BADDR int 0x0 Base address of SAU region51 at reset
SAU_REGION51.ENABLE bool 0x0 Enable SAU region51 at reset
SAU_REGION51.LADDR int 0x0 Limit address of SAU region51 at reset
SAU_REGION51.NSC bool 0x0 Set NSC for SAU region51 at reset
SAU_REGION52.BADDR int 0x0 Base address of SAU region52 at reset
SAU_REGION52.ENABLE bool 0x0 Enable SAU region52 at reset
SAU_REGION52.LADDR int 0x0 Limit address of SAU region52 at reset
SAU_REGION52.NSC bool 0x0 Set NSC for SAU region52 at reset
SAU_REGION53.BADDR int 0x0 Base address of SAU region53 at reset
SAU_REGION53.ENABLE bool 0x0 Enable SAU region53 at reset
SAU_REGION53.LADDR int 0x0 Limit address of SAU region53 at reset
SAU_REGION53.NSC bool 0x0 Set NSC for SAU region53 at reset
SAU_REGION54.BADDR int 0x0 Base address of SAU region54 at reset
SAU_REGION54.ENABLE bool 0x0 Enable SAU region54 at reset
SAU_REGION54.LADDR int 0x0 Limit address of SAU region54 at reset
SAU_REGION54.NSC bool 0x0 Set NSC for SAU region54 at reset
SAU_REGION55.BADDR int 0x0 Base address of SAU region55 at reset
SAU_REGION55.ENABLE bool 0x0 Enable SAU region55 at reset
SAU_REGION55.LADDR int 0x0 Limit address of SAU region55 at reset
SAU_REGION55.NSC bool 0x0 Set NSC for SAU region55 at reset
SAU_REGION56.BADDR int 0x0 Base address of SAU region56 at reset
SAU_REGION56.ENABLE bool 0x0 Enable SAU region56 at reset
SAU_REGION56.LADDR int 0x0 Limit address of SAU region56 at reset
SAU_REGION56.NSC bool 0x0 Set NSC for SAU region56 at reset
SAU_REGION57.BADDR int 0x0 Base address of SAU region57 at reset
SAU_REGION57.ENABLE bool 0x0 Enable SAU region57 at reset
SAU_REGION57.LADDR int 0x0 Limit address of SAU region57 at reset
SAU_REGION57.NSC bool 0x0 Set NSC for SAU region57 at reset
SAU_REGION58.BADDR int 0x0 Base address of SAU region58 at reset
SAU_REGION58.ENABLE bool 0x0 Enable SAU region58 at reset
SAU_REGION58.LADDR int 0x0 Limit address of SAU region58 at reset
SAU_REGION58.NSC bool 0x0 Set NSC for SAU region58 at reset
SAU_REGION59.BADDR int 0x0 Base address of SAU region59 at reset
SAU_REGION59.ENABLE bool 0x0 Enable SAU region59 at reset
SAU_REGION59.LADDR int 0x0 Limit address of SAU region59 at reset
SAU_REGION59.NSC bool 0x0 Set NSC for SAU region59 at reset
SAU_REGION6.BADDR int 0x0 Base address of SAU region6 at reset
SAU_REGION6.ENABLE bool 0x0 Enable SAU region6 at reset
SAU_REGION6.LADDR int 0x0 Limit address of SAU region6 at reset
SAU_REGION6.NSC bool 0x0 Set NSC for SAU region6 at reset
SAU_REGION60.BADDR int 0x0 Base address of SAU region60 at reset
SAU_REGION60.ENABLE bool 0x0 Enable SAU region60 at reset
SAU_REGION60.LADDR int 0x0 Limit address of SAU region60 at reset
SAU_REGION60.NSC bool 0x0 Set NSC for SAU region60 at reset
SAU_REGION61.BADDR int 0x0 Base address of SAU region61 at reset
SAU_REGION61.ENABLE bool 0x0 Enable SAU region61 at reset
SAU_REGION61.LADDR int 0x0 Limit address of SAU region61 at reset
SAU_REGION61.NSC bool 0x0 Set NSC for SAU region61 at reset
SAU_REGION62.BADDR int 0x0 Base address of SAU region62 at reset
SAU_REGION62.ENABLE bool 0x0 Enable SAU region62 at reset
SAU_REGION62.LADDR int 0x0 Limit address of SAU region62 at reset
SAU_REGION62.NSC bool 0x0 Set NSC for SAU region62 at reset
SAU_REGION63.BADDR int 0x0 Base address of SAU region63 at reset
SAU_REGION63.ENABLE bool 0x0 Enable SAU region63 at reset
SAU_REGION63.LADDR int 0x0 Limit address of SAU region63 at reset
SAU_REGION63.NSC bool 0x0 Set NSC for SAU region63 at reset
SAU_REGION64.BADDR int 0x0 Base address of SAU region64 at reset
SAU_REGION64.ENABLE bool 0x0 Enable SAU region64 at reset
SAU_REGION64.LADDR int 0x0 Limit address of SAU region64 at reset
SAU_REGION64.NSC bool 0x0 Set NSC for SAU region64 at reset
SAU_REGION65.BADDR int 0x0 Base address of SAU region65 at reset
SAU_REGION65.ENABLE bool 0x0 Enable SAU region65 at reset
SAU_REGION65.LADDR int 0x0 Limit address of SAU region65 at reset
SAU_REGION65.NSC bool 0x0 Set NSC for SAU region65 at reset
SAU_REGION66.BADDR int 0x0 Base address of SAU region66 at reset
SAU_REGION66.ENABLE bool 0x0 Enable SAU region66 at reset
SAU_REGION66.LADDR int 0x0 Limit address of SAU region66 at reset
SAU_REGION66.NSC bool 0x0 Set NSC for SAU region66 at reset
SAU_REGION67.BADDR int 0x0 Base address of SAU region67 at reset
SAU_REGION67.ENABLE bool 0x0 Enable SAU region67 at reset
SAU_REGION67.LADDR int 0x0 Limit address of SAU region67 at reset
SAU_REGION67.NSC bool 0x0 Set NSC for SAU region67 at reset
SAU_REGION68.BADDR int 0x0 Base address of SAU region68 at reset
SAU_REGION68.ENABLE bool 0x0 Enable SAU region68 at reset
SAU_REGION68.LADDR int 0x0 Limit address of SAU region68 at reset
SAU_REGION68.NSC bool 0x0 Set NSC for SAU region68 at reset
SAU_REGION69.BADDR int 0x0 Base address of SAU region69 at reset
SAU_REGION69.ENABLE bool 0x0 Enable SAU region69 at reset
SAU_REGION69.LADDR int 0x0 Limit address of SAU region69 at reset
SAU_REGION69.NSC bool 0x0 Set NSC for SAU region69 at reset
SAU_REGION7.BADDR int 0x0 Base address of SAU region7 at reset
SAU_REGION7.ENABLE bool 0x0 Enable SAU region7 at reset
SAU_REGION7.LADDR int 0x0 Limit address of SAU region7 at reset
SAU_REGION7.NSC bool 0x0 Set NSC for SAU region7 at reset
SAU_REGION70.BADDR int 0x0 Base address of SAU region70 at reset
SAU_REGION70.ENABLE bool 0x0 Enable SAU region70 at reset
SAU_REGION70.LADDR int 0x0 Limit address of SAU region70 at reset
SAU_REGION70.NSC bool 0x0 Set NSC for SAU region70 at reset
SAU_REGION71.BADDR int 0x0 Base address of SAU region71 at reset
SAU_REGION71.ENABLE bool 0x0 Enable SAU region71 at reset
SAU_REGION71.LADDR int 0x0 Limit address of SAU region71 at reset
SAU_REGION71.NSC bool 0x0 Set NSC for SAU region71 at reset
SAU_REGION72.BADDR int 0x0 Base address of SAU region72 at reset
SAU_REGION72.ENABLE bool 0x0 Enable SAU region72 at reset
SAU_REGION72.LADDR int 0x0 Limit address of SAU region72 at reset
SAU_REGION72.NSC bool 0x0 Set NSC for SAU region72 at reset
SAU_REGION73.BADDR int 0x0 Base address of SAU region73 at reset
SAU_REGION73.ENABLE bool 0x0 Enable SAU region73 at reset
SAU_REGION73.LADDR int 0x0 Limit address of SAU region73 at reset
SAU_REGION73.NSC bool 0x0 Set NSC for SAU region73 at reset
SAU_REGION74.BADDR int 0x0 Base address of SAU region74 at reset
SAU_REGION74.ENABLE bool 0x0 Enable SAU region74 at reset
SAU_REGION74.LADDR int 0x0 Limit address of SAU region74 at reset
SAU_REGION74.NSC bool 0x0 Set NSC for SAU region74 at reset
SAU_REGION75.BADDR int 0x0 Base address of SAU region75 at reset
SAU_REGION75.ENABLE bool 0x0 Enable SAU region75 at reset
SAU_REGION75.LADDR int 0x0 Limit address of SAU region75 at reset
SAU_REGION75.NSC bool 0x0 Set NSC for SAU region75 at reset
SAU_REGION76.BADDR int 0x0 Base address of SAU region76 at reset
SAU_REGION76.ENABLE bool 0x0 Enable SAU region76 at reset
SAU_REGION76.LADDR int 0x0 Limit address of SAU region76 at reset
SAU_REGION76.NSC bool 0x0 Set NSC for SAU region76 at reset
SAU_REGION77.ENABLE bool 0x0 Enable SAU region77 at reset
SAU_REGION8.BADDR int 0x0 Base address of SAU region8 at reset
SAU_REGION8.ENABLE bool 0x0 Enable SAU region8 at reset
SAU_REGION8.LADDR int 0x0 Limit address of SAU region8 at reset
SAU_REGION8.NSC bool 0x0 Set NSC for SAU region8 at reset
SAU_REGION9.BADDR int 0x0 Base address of SAU region9 at reset
SAU_REGION9.ENABLE bool 0x0 Enable SAU region9 at reset
SAU_REGION9.LADDR int 0x0 Limit address of SAU region9 at reset
SAU_REGION9.NSC bool 0x0 Set NSC for SAU region9 at reset
SAU_TYPE.SREGION int 0x10 Number of SAU regions (0 => no SAU)
VTOR_NS bool 0x1 NonSecure Vector Table Offset Register is writeable
VTOR_NS_MASK int 0xffffff80 Non-Secure VTOR write mask
VTOR_S bool 0x1 Secure Vector Table Offset Register is writeable
VTOR_S_MASK int 0xffffff80 Secure VTOR write mask
allow_stack_accesses_to_ppb_space bool 0x0 Allow stack accesses to PPB space
cpi_div int 0x1 divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 multiplier for calculating CPI (Cycles Per Instruction)
dcache-invalidate-ns-cleans-s bool 0x0 Whether V8M DCI* in non-secure should clean-and-invalidate secure cache contents.
dcache-size int 0x8000 L1 D-cache size in bytes
dcache-state_modelled bool 0x0 Set whether D-cache has stateful implementation
dcache-ways int 0x4 L1 D-cache ways (sets are implicit from size)
dtcm_enable bool 0x0 Enable DTCM at reset
dtcm_size int 0x100 DTCM size in KB
duplicate_CADI_TCM_writes bool 0x0 CADI writes to TCMs are also sent to downstream memory at same addresses (for validation platforms)
exercise_strex_fail bool 0x0 Reject a pseudo-random majority of exclusive store instructions
has_writebuffer bool 0x0 Implement write accesses buffering before L1 cache. May affect ext_abort behaviour.
icache-size int 0x8000 L1 I-cache size in bytes
icache-state_modelled bool 0x0 Set whether I-cache has stateful implementation
icache-ways int 0x2 L1 I-cache ways (sets are implicit from size)
ignore_RNR_top_nibble bool 0x0 If set, only the bottom four bits of MPU_RNR.REGION are used
ignore_out_of_range_RNR_write bool 0x0 If an MPU_RNR.REGION write is out of range, ignore it ; if false, MPU_RNR values wrap
itcm_enable bool 0x0 Enable ITCM at reset
itcm_size int 0x100 ITCM size in KB
master_id int 0x0 Master ID presented in bus transactions
min_sync_level int 0x0 force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
number_of_itm_stimulus_ports int 0x20 The number of ITM stimulus ports
rd_ns_bus_err_behave int 0x1 External read aborts in nonsecure domain 0:ignored, 1:precise, 2:imprecise, 3=imprecise except SO.
rd_s_bus_err_behave int 0x1 External read aborts in secure domain 0:ignored, 1:precise, 2:imprecise, 3=imprecise except SO.
scheduler_mode int 0x0 Control the interleaving of instructions in this processor (0=default long quantum, 1=low latency mode, short quantum and signal checking, 2=lock-breaking mode, long quantum with additional context switches near load-exclusive instructions, 3=ISSCompare)
semihosting-Thumb_SVC int 0xab T32 SVC number for semihosting
semihosting-cmd_line string "" Command line available to semihosting SVC calls
semihosting-cwd string "" Base directory for semihosting file access.
semihosting-enable bool 0x1 Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
semihosting-heap_base int 0x0 Virtual address of heap base
semihosting-heap_limit int 0x10700000 Virtual address of top of heap
semihosting-prefix bool 0x0 Prefix semihosting output with target instance name
semihosting-stack_base int 0x10700000 Virtual address of base of descending stack
semihosting-stack_limit int 0x10800000 Virtual address of stack limit
vfp-enable_at_reset bool 0x0 Enable VFP in CPACR, CPPWR, NSACR at reset. Warning: Arm recommends going through the implementation's suggested VFP power-up sequence!
vfp-present bool 0x1 Set whether the model has VFP support
wr_ns_bus_err_behave int 0x3 External write aborts in nonsecure domain 0:ignored, 1:precise, 2:imprecise, 3=imprecise except SO.
wr_s_bus_err_behave int 0x3 External write aborts in secure domain 0:ignored, 1:precise, 2:imprecise, 3=imprecise except SO.
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