5.15.14 Tarmac Trace output example

This is an example of a trace that was produced by the Tarmac Trace plug-in, showing instruction, register, event, and memory access traces.

1939 clk cpu0 IT (1915) 0001129c:00001521129c d51bd061 O EL3h_s : MSR TPIDRRO_EL0,x1
1939 clk cpu0 R TPIDRRO_EL0 00000000:00000000
1940 clk cpu0 IT (1916) 000112a0:0000152112a0 d001c100 O EL3h_s : ADRP x0,{pc}+0x3822000 ; 0x38332a0
1940 clk cpu0 R X0 0000000003833000
1941 clk cpu0 IT (1917) 000112a4:0000152112a4 91024000 O EL3h_s : ADD x0,x0,#0x90
1941 clk cpu0 R X0 0000000003833090
1942 clk cpu0 IT (1918) 000112a8:0000152112a8 d2810002 O EL3h_s : MOV x2,#0x800
1942 clk cpu0 R X2 0000000000000800
1943 clk cpu0 IT (1919) 000112ac:0000152112ac 91000421 O EL3h_s : ADD x1,x1,#1
1943 clk cpu0 R X1 0000000000000001
1944 clk cpu0 IT (1920) 000112b0:0000152112b0 9b017c42 O EL3h_s : MUL x2,x2,x1
1944 clk cpu0 R X2 0000000000000800
1945 clk cpu0 IT (1921) 000112b4:0000152112b4 8b020000 O EL3h_s : ADD x0,x0,x2
1945 clk cpu0 R X0 0000000003833890
1946 clk cpu0 IT (1922) 000112b8:0000152112b8 9100001f O EL3h_s : MOV sp,x0
1946 clk cpu0 R SP_EL3 0000000003833890
1947 clk cpu0 IT (1923) 000112bc:0000152112bc 10001420 O EL3h_s : ADR x0,{pc}+0x284 ; 0x11540
1947 clk cpu0 R X0 0000000000011540
1947 clk cpu0 CACHE cpu.cpu0.l1icache LINE 0096 ALLOC 0x0000152112c0
1947 clk cpu0 CACHE Validation_ARMAEMv8AMPCT.cpu.l2_cache LINE 04b0 ALLOC 0x0000152112c0
1948 clk cpu0 IT (1924) 000112c0:0000152112c0 f9400000 O EL3h_s : LDR x0,[x0,#0]
1948 clk cpu0 MR8 00011540:000015211540 00000000_13000000
1948 clk cpu0 R X0 0000000013000000
1948 clk cpu0 CACHE cpu.cpu0.l1dcache LINE 00aa ALLOC 0x000015211540
1948 clk cpu0 CACHE Validation_ARMAEMv8AMPCT.cpu.l2_cache LINE 0550 ALLOC 0x000015211540
1949 clk cpu0 IT (1925) 000112c4:0000152112c4 d0000081 O EL3h_s : ADRP x1,{pc}+0x12000 ; 0x232c4
1949 clk cpu0 R X1 0000000000023000
1950 clk cpu0 IT (1926) 000112c8:0000152112c8 91017021 O EL3h_s : ADD x1,x1,#0x5c
1950 clk cpu0 R X1 000000000002305C
1951 clk cpu0 IT (1927) 000112cc:0000152112cc d63f0020 O EL3h_s : BLR x1
1951 clk cpu0 R X30 00000000000112D0
1951 clk cpu0 TTW ITLB LPAE 1:3 000016390010 00000000152204c3 : BLOCK ATTRIDX=0 NS=0 AP=3 SH=0 AF=1 nG=0 16E=0 PXN=0 XN=0 ADDR=0x0000000015220000
1951 clk cpu0 TLB FILL cpu.cpu0.ITLB 64K 0x00020000, nG asid=0:0x0015220000 Normal NonShareable Inner=WriteBackWriteAllocate Outer=WriteBackWriteAllocate xn=0 pxn=0 ContiguousHint =0
1951 clk cpu0 TLB FILL cpu.cpu0.S1TLB 64K 0x00020000, nG asid=0:0x0015220000 Normal NonShareable Inner=WriteBackWriteAllocate Outer=WriteBackWriteAllocate xn=0 pxn=0 ContiguousHint =0
1951 clk cpu0 CACHE cpu.cpu0.l1icache LINE 0182 ALLOC 0x000015223040
1951 clk cpu0 CACHE Validation_ARMAEMv8AMPCT.cpu.l2_cache LINE 0c10 ALLOC 0x000015223040
1952 clk cpu0 IT (1928) 0002305c:00001522305c f0030f48 O EL3h_s : ADRP x8,{pc}+0x61eb000 ; 0x620e05c
1952 clk cpu0 R X8 000000000620E000
1953 clk cpu0 IT (1929) 00023060:000015223060 f9000100 O EL3h_s : STR x0,[x8,#0]
1953 clk cpu0 TTW DTLB LPAE 1:3 000016393100 0000000016000463 : BLOCK ATTRIDX=0 NS=1 AP=1 SH=0 AF=1 nG=0 16E=0 PXN=0 XN=0 ADDR=0x0000000016000000
1953 clk cpu0 MW8 0620e000:00001600e000_NS 00000000_13000000
1953 clk cpu0 TLB FILL cpu.cpu0.DTLB 64K 0x06200000, nG asid=0:0x0016000000_NS Normal NonShareable Inner=WriteBackWriteAllocate Outer=WriteBackWriteAllocate xn=0 pxn=0 ContiguousHint =0
1953 clk cpu0 TLB FILL cpu.cpu0.S1TLB 64K 0x06200000, nG asid=0:0x0016000000_NS Normal NonShareable Inner=WriteBackWriteAllocate Outer=WriteBackWriteAllocate xn=0 pxn=0 ContiguousHint =0
1953 clk cpu0 CACHE cpu.cpu0.l1dcache LINE 0188 ALLOC 0x000016393100
1953 clk cpu0 CACHE Validation_ARMAEMv8AMPCT.cpu.l2_cache LINE 0c40 ALLOC 0x000016393100
1954 clk cpu0 IT (1930) 00023064:000015223064 17fffff5 O EL3h_s : B {pc}-0x2c ; 0x23038
1954 clk cpu0 CACHE cpu.cpu0.l1icache LINE 0180 ALLOC 0x000015223000
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